Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will
be left disabled. Linux does not set up this routing but relies upon it
having been set up by the bootloader, reading back the IRQ lines which
the PIRQ[A:D] signals have been routed to.
This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11.
This matches the setup used by YAMON.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Displaying a message on the LCD screen is a simple yet effective way to
show the user that the board has booted successfully.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.
Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.
Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This is in preparation for adapting this board to function correctly on
a physical MIPS Malta board. The board is moved into an "imgtec" vendor
directory at the same time in order to ready us for any other boards
supported by Imagination in the future.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
For boards such as the MIPS Malta with an FPGA core card it is desirable
to be able to detect the L1 cache sizes at runtime, since they are not
dependant upon the board but on the FPGA bitstream in use. This patch
performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are
not defined by the board configuration. In cases where the sizes are
detected this patch also removes the restriction that the I-cache &
D-cache line sizes must be the same, as this is not necessarily true.
If the cache sizes are defined by a configuration then they will be
hardcoded as before, so this patch will not add overhead to such
boards.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)
We don't need to provide Linux copatibility any more.
This commit deletes include/linux/config.h
and fixes source files not to include this.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
arch/sparc/cpu/leon3/start.S requires CONFIG_SYS_SPARC_NWINDOES
to be defined:
#ifndef CONFIG_SYS_SPARC_NWINDOWS
#error Must define number of SPARC register windows, default is 8
#endif
But it missed to include <config.h>, which always ended up in compile error.
This commit fixes this problem.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
Convert sh to use the commmon timer code. Remove reset_timer and
set_timer as they are unused on sh.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
The gpio register mappings are different among blackfin processors.
Signed-off-by: Steven Miao <realmz6@gmail.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
This commit fixes:
cpu.c:107: warning: ‘noreturn’ function does return
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Before this commit, arch/sparc/lib/Makefile used
both COBJS and COBJS-y.
And it missed to add COBJS-y into OBJS.
This means bootm.o was never compiled even if
CONFIG_CMD_BOOTM=y
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Daniel Hellstrom <daniel@gaisler.com>
This patch moves S5PC, EXYNOS specific directory entries
from the toplevel Makefile to arch/arm/cpu/armv7/Makefile
using Kbuild descending feature.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
This patch moves OMAP specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/armv7/Makefile using Kbuild descending feature.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
This patch moves Tegra specific directory entries
from the toplevel Makefile and spl/Makefile
to arch/arm/cpu/*/Makefile using Kbuild descending feature.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Warren <TWarren@nvidia.com>
Note:
arch/powerpc/cpu/mpc8260/Makefile is originally like follows:
---<snip>---
START = start.o kgdb.o
COBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
---<snip>---
COBJS-$(CONFIG_ETHER_ON_SCC) = ether_scc.o
---<snip>---
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)
The link rule `$(call cmd_link_o_target, $(OBJS) $(obj)kgdb.o)'
is weird.
kbdg.o is not included in $(OBJS) but linked into $(LIB)
and $(LIB) is not dependent on kgdb.o.
(Broken dependency tracking)
So,
START = start.o kgdb.o
shoud have been
START = start.o
SOBJS = kgdb.o
That is why this commit adds kgdb.o to obj-y, not to extra-y.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Multiple targets are included in arch/arm/imx-common/Makefile
In order to refactor it,
we need to tweak Makefile and spl/Makefile.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Note1:
In arch/arm/cpu/arm926ejs/spear/Makefile
START := start.o
was changed
extra-$(CONFIG_SPL_BUILD) := start.o
because spear/start.o is only used for SPL.
Note2:
START := start.o
was missing from arch/arm/cpu/arm926ejs/mxs/Makefile.
This commit simply adds
extra-$(CONFIG_SPL_BUILD) := start.o
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
This allows to share some common code for the boards that use a corenet
base SoC.
Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix t1040qds.c]
Acked-by: York Sun <yorksun@freescale.com>
If the DDR3 module supports industrial temperature range and requires
the x2 refresh rate for that temp range, the refresh period must be
3.9us instead of 7.8 us.
This was successfuly tested on kmp204x board with some MT41K128M16 DDR3
RAM chips (no module used, chips directly soldered on board with an SPD
EEPROM).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix minor conflicts in fsl_ddr_dimm_params.h,
lc_common_dimm_params.c, common_timing_params.h]
Acked-by: York Sun <yorksun@freescale.com>
When exporting the new memsize without reserved PRAM area, the -Wformat
option produces a warning since %ld is used for snprintf and bi_memsize
is phys_size_t.
This patch removes this warning for all PRAM PowerPC boards.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Introduce different macros for storing addresses of multiple
USB controllers. This is required for successful initialization
and usage of multiple USB controllers inside u-boot
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
CONFIG_USB_MAX_CONTROLLER_COUNT macro recently defined for
initializing all USB controllers on a given platform. This
macro is defined for all 85xx socs
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
