Commit graph

52143 commits

Author SHA1 Message Date
Vikas Manocha
6c0c3ce8aa serial: stm32f7: disable overrun
With overrun enabled, serial port console freezes & stops receiving data with
overun error if we keep sending data.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-09 11:23:59 -04:00
Vikas Manocha
c6d9e9dbc3 SPL: Add XIP booting support
Enable support for XIP (execute in place) of U-Boot or kernel image. There is
no need to copy image from flash to ram if flash supports execute in place.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Alexandru Gagniuc <alex.g@adaptrum.com>
2017-06-09 11:23:59 -04:00
Vikas Manocha
b97476965b stm32: stm32f7: add spl build support
This commit supports booting from stm32 internal nor flash. spl U-Boot
initializes the sdram memory, copies next image (e.g. standard U-Boot)
to sdram & then jumps to entry point.

Here are the flash memory addresses for U-Boot-spl & standard U-Boot:
	- spl U-Boot		: 0x0800_0000
	- standard U-Boot	: 0x0800_8000

To compile u-boot without spl: Remove SUPPORT_SPL configuration
(arch/arm/mach-stm32/Kconfig)

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
[trini: Rework Kconfig logic a bit]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-09 11:23:55 -04:00
Philipp Tomsich
76a5e1b715 rockchip: video: document externally visible functions for rk_vop
Documents the externally visible functions shared between the VOP
drivers for the RK3288 and RK3399.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:57:25 +02:00
Philipp Tomsich
56c7ba3462 rockchip: video: document externally visible functions for rk_hdmi
Documents the externally visible functions shared between the HDMI
drivers for the RK3288 and RK3399.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:53:48 +02:00
Wenyou Yang
31e5c892b3 video: atmel_hlcdfb: Fix misaligned cache operation warning
Fix the warning,
 ---8<---
CACHE: Misaligned operation at range [3fdffff0, 3fdffffc]
 ---<8---

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:33:28 +02:00
Jernej Skrabec
b98efa1db3 sunxi: video: Add support for CSC and TVE to DE2 driver
Extend DE2 driver with support for TVE driver, which will be added in
next commit. TVE unit expects data to be in YUV format, so CSC support
is also added here.

Note that HDMI driver has higher priority, so TV out is not probed if
HDMI monitor is detected.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:30:47 +02:00
Jernej Skrabec
a8191dfec0 sunxi: Add base address for TV encoder
This commit adds TVE base address for Allwinner H3 and H5 SoCs.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-06-09 15:30:28 +02:00
Jernej Skrabec
af4c874f11 sunxi: video: Rename tve.c to tve_common.c
In order to avoid future confusion with similary named files, rename
tve.c to tve_common.c. New name better represents the fact that this file
holds code which can be and will be shared between multiple drivers.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:30:13 +02:00
Jernej Skrabec
bdc906dba9 edid: Fix gcc 7.1 warning
This commit fixes the warning produced by gcc 7.1.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 15:29:59 +02:00
Brock Zheng Techyauld Ltd
abf54bf978 Fixup bug in PMIC TPS65217 register address definition
The addresses of the registers in TI TPS65217 are not continuous.
     There is a gap between ENABLE(0x16) and DEFUVLO(0x18). No 0x17
     register available.

     Fixup the enum values by adding a 'reserved' placeholder to correct
     the addresses higher than 0x17.

     Series-to: Heiko Schocher <hs@denx.de>

Signed-off-by: Brock Zheng Techyauld Ltd <yzheng@techyauld.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2017-06-09 20:25:16 +09:00
Keerthy
2dd9dc02a3 power: regulator: lp87565: add regulator support
The driver provides regulator set/get voltage
enable/disable functions for lp87565 family of PMICs.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-09 20:25:16 +09:00
Keerthy
cdad57a7c1 power: pmic: lp87565: Add the basic pmic support
Add support to bind the regulators/child nodes with the pmic.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-09 20:25:16 +09:00
Simon Glass
9752564722 dm: mmc: Avoid probing block devices in find_mmc_device()
We do not need to probe the block device here, so avoid doing so. The MMC
device itself must be active, but the block device can come later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 20:25:16 +09:00
Simon Glass
01b73fe630 dm: mmc: Ensure that block device is probed
Make sure that we probe the block device before using it when reading
the environment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-09 20:25:16 +09:00
Simon Glass
9f103b9cb5 dm: blk: Add a way to obtain a block device from its parent
Many devices support a child block device (e.g. MMC, USB). Add a
convenient way to get this device given the parent device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-06-09 20:25:16 +09:00
Keerthy
fc69d47262 board: ti: AM43XX: Add ddr voltage rail configuration
Add ddr voltage rail (dcdc3) configuration. Set the dcdc3
DDR supply to 1.35V.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-06-09 20:25:16 +09:00
Keerthy
e395b8848a power: pmic: tps65218: Add DCDC3 configuration
Some boards like am437x-gp-evm require dcdc3 also to be configured
as it feeds on to ddr. Hence add the capability as well.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-06-09 20:25:16 +09:00
Keerthy
75bceb22b3 power: regulator: palmas: Add smps12 dual regulator for tps65917
Add smps12 dual regulator for tps65917

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-09 20:25:16 +09:00
Marek Vasut
0f53118511 mmc: sh_sdhi: Fix Kconfig entry
The Kconfig entry depends on RMOBILE, but this was renamed
to ARCH_RMOBILE in commit 1cc95f6e1b (ARM: Rmobile: Rename
CONFIG_RMOBILE to CONFIG_ARCH_RMOBILE) . Fix this omission.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-09 20:25:16 +09:00
Kouei Abe
a5950f8dfb mmc: sh_sdhi: Add SDHI support
R-Car Gen3 series have four SD card interfaces (SDHI0 to SDHI3),
two of which can also be used as MMC interfaces (SDHI2 and SDHI3).
This adds High-speed mode SD clock frequency between 25MHz and 50MHz,
8bit/4bit bus width, high capacity and low voltage device support.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-09 20:25:16 +09:00
Kouei Abe
91a16c3b2f mmc: sh_sdhi: Add MMC version 5.0 support
Renesas SDHI SD/MMC driver did not support MMC version 5.0 devices.
This adds MMC version 5.0 device support.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-06-09 20:25:16 +09:00
Kouei Abe
5eada1dbd0 mmc: sh_sdhi: Add 64-bit access to sd_buf support
Renesas SDHI SD/MMC driver has 16-bit width bus access to SD_BUF.
This adds 64-bit width bus access to SD_BUF.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-09 20:25:16 +09:00
Kouei Abe
3ebc62c987 mmc: sh_sdhi: Set SD_INFOx interrupt mask before command starting
When setting interrupt mask after command starting, an unintended
interrupt status sometimes occurs.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2017-06-09 20:25:16 +09:00
Simon Glass
6e87ae1c07 patman: Add a functional test
The existing test (patman --test) only covers basic checkpatch output.
We have had some problems with unicode processing and could use test
coverage for the various tags patman supports.

Add a new functional test which runs most of the patman flow on a few
test commits and checks that the results are correct.

See the documentation in the test for a description of what it does.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
a44f4fb72b patman: Rename 'list' variable in MakeCcFile()
This is not a good variable name in Python because 'list' is a type. It
shows up highlighted in some editors. Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
1f487f85d2 patman: Add a maintainer test feature to MakeCcFile()
Allow the add_maintainers parameter to be a list of maintainers, thus
allowing us to simulate calling the script in tests without actually
needing it to work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
2eb5fc13b3 patman: Add unicode to test patches
Add some unicode to the test patches to make sure that patman does the
right thing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
db116cc8d0 patman: Don't return the series in FixPatches()
There is no need for this function to return the same object that was
passed in. Drop the return value.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
04f7870635 patman: Don't report unicode character
Unicode characters may appear in input patches so we should not warn about
them. Drop this warning.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
2df3a01974 patman: Rename 'str' variable in EmailPatches()
This is not a good variable name in Python because 'str' is a type. It
shows up highlighted in some editors. Rename it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
5c724dc440 patman: Don't convert input data to unicode
The communication filter reads data in blocks and converts each block to
unicode (if necessary) one at a time. In the unlikely event that a unicode
character in the input spans a block this will not work. We get an error
like:

UnicodeDecodeError: 'utf8' codec can't decode bytes in position 1022-1023:
   unexpected end of data

There is no need to change the input to unicode, so the easiest fix is to
drop this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Simon Glass
6f8abf765b patman: Adjust handling of unicode email address
Don't mess with the email address when outputting them. Just make sure
they are encoded with utf-8.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Philipp Tomsich
21caa558ca patman: encode CC list to UTF-8
This change encodes the CC list to UTF-8 to avoid failures on
maintainer-addresses that include non-ASCII characters (observed on
Debian 7.11 with Python 2.7.3).

Without this, I get the following failure:
  Traceback (most recent call last):
    File "tools/patman/patman", line 159, in <module>
      options.add_maintainers)
    File "[snip]/u-boot/tools/patman/series.py", line 234, in MakeCcFile
      print(commit.patch, ', '.join(set(list)), file=fd)
  UnicodeEncodeError: 'ascii' codec can't encode character u'\xfc' in position 81: ordinal not in range(128)
from Heiko's email address:
  [..., u'"Heiko St\xfcbner" <heiko@sntech.de>', ...]

While with this change added this encodes to:
  "=?UTF-8?q?Heiko=20St=C3=BCbner?= <heiko@sntech.de>"

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-08 20:21:59 -06:00
Tom Rini
d5686a61d6 buildman: Fix bloat option when 'new' only drops functions
In the case where a new build only decreases sizes and does not increase
any size we still want to report what functions have been dropped when
doing a bloat comparison.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-08 20:21:59 -06:00
Tom Rini
e2bc87d41c sandbox: Fix comparison of unsigned enum expression warning
In os_dirent_get_typename() we are checking that type falls within the
known values of the enum os_dirent_t.  With clang-3.8 testing this value
as being >= 0 results in a warning as it will always be true.  This
assumes of course that we are only given valid data.  Given that we want
to sanity check the input, we change this to check that it falls within
the range of the first to the last entry in the given enum.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-08 20:21:59 -06:00
Vikas Manocha
ea744fca0e stm32f7: remove duplicate configs
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-08 21:00:27 -04:00
Vikas Manocha
6bcdd66d1c spl: armv7m: to keep ARM v7M in thumb mode before booting next image
On ARM v7M, the processor will return to ARM mode when executing blx
instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb
mode.

At present, it is applied only for raw U-Boot. This patch moves it to just
before booting next image. This way armv7m will be in thumb mode for any image
like raw or image with header like zImage or standard U-Boot.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-06-08 21:00:27 -04:00
Icenowy Zheng
84580628b8 sunxi: add a defconfig for SoPine w/ official baseboard
The SoPine is a SoM by Pine64, with an Allwinner A64 SoC, a LPDDR3 DRAM
chip, an AXP803 PMIC, a SPI NOR Flash and a MicroSD slot. The card
detect pin of the MicroSD slot is broken, however, it doesn't matter as
the design of SoPine didn't allow hot-swapping the MicroSD card (The
MicroSD slot is at the back of the SoM, and when the SoM is installed on
the baseboard, it's nearly impossible to remove the MicroSD).

The official baseboard of it is a board with nearly the same connectors
with the original Pine64+, with the MicroUSB power jack replaced, and
at the position of MicroSD slot a eMMC module slot is added.

Add support for SoPine with the official baseboard by adding its
defconfig file. It still uses the device tree of Pine64, however, it
will change after a proper device tree of SoPine with baseboard is
accepted by Linux mainline.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
[Update board/sunxi/MAINTAINERS]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
ec4670a137 sunxi: add LPDDR3 timing from stock boot0
As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.

Add the timing info used by stock boot0.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
72cc987002 sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.

Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.

Real LPDDR3 chips' support is not added yet in this commit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
7d06e59f73 sunxi: enable DRAM initialization and SPL for V3s SoC
As we have already support for the DesignWare DRAM controller and the
integrated DDR2 chip of V3s, let's enable the SPL support for V3s.

This patch also contains the default DRAM configuration for V3s.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
3ec0698b8a sunxi: add support for V3s DRAM controller
Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
67337e68a5 sunxi: add support for the DDR2 in V3s SoC
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
176868bc65 sunxi: enable dual rank detection in DesignWare-like DRAM code
The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.

Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.

Currently we know little about the dual-rank on R40, and the usage
of A15 address line seems to be breaking dual-rank support. The only R40
board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather
than dual-rank, thus we cannot do research for it. So dual rank detection
is temporarily disabled on R40.

This change is tested on a Orange Pi One (H3, single rank), a Pine64+
2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
on one chip).

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
f6457ce578 sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.

Add options to select a timing set.

Currently only DDR3-1333 (the original set) is added into it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
66b12526f0 sunxi: add bank detection code to H3 DRAM initialization code
Some DDR2 DRAM have only four banks, not eight.

Add code to detect this situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
87098d701d sunxi: add option for 16-bit DW DRAM controller
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.

Add support for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
f43a009959 sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.

As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.

Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.

This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30
Icenowy Zheng
9934aba427 sunxi: makes an invisible option for H3-like DRAM controllers
Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like
DesignWare DRAM controller, which do not have official free DRAM
initialization code, but can use modified dram_sun8i_h3.c.

Add a invisible option for easier DRAM initialization code reuse.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2017-06-08 22:37:55 +05:30