Commit graph

579 commits

Author SHA1 Message Date
Patrick Delaunay
9f2b066cda gpio: add gpio descriptor initialization helper
Add a helper function gpio_desc_init() to initialize the gpio descriptor;
with this function the flags will be always set to 0.

It wasn't the case before this patch in dm_gpio_lookup_name.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-16 23:06:54 -04:00
Patrick Delaunay
e3f3a121d8 gpio: remove the open_drain API and ops
This patch removes the ops get_open_drain/set_open_drain
and the API dm_gpio_get_open_drain/dm_gpio_set_open_drain.

The ops only provided in one driver (mpc8xxx gpio) and the
associated API is never called in boards.

This patch prepare a more generic set/get_dir_flags ops,
including the open drain property.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-16 23:06:54 -04:00
Klaus H. Sorensen
3fb22bc2f8 gpio/mpc83xx_spisel_boot.c: gpio driver for SPISEL_BOOT signal
Some SoCs in the mpc83xx family, e.g. mpc8309, have a dedicated spi
chip select, SPISEL_BOOT, that is used by the boot code to boot from
flash.

This chip select will typically be used to select a SPI boot
flash. The SPISEL_BOOT signal is controlled by a single bit in the
SPI_CS register.

Implement a gpio driver for the spi chip select register. This allows a
spi driver capable of using gpios as chip select, to bind a chip select
to SPISEL_BOOT.

It may be a little odd to do this as a GPIO driver, since the signal
is neither GP or I, but it is quite convenient to present it to the
spi driver that way. The alternative it to teach mpc8xxx_spi to handle
the SPISEL_BOOT signal itself (that is how it's done in the linux
kernel, see commit 69b921acae8a)

Signed-off-by: Klaus H. Sorensen <khso@prevas.dk>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Rasmus Villemoes
dd4cf53f98 gpio: mpc8xxx: don't do RMW on gpdat register when setting value
The driver correctly handles reading back the value of an output gpio
by reading from the shadow register for output, and from gpdat for
inputs.

Unfortunately, when setting the value of some gpio, we do a RMW cycle
on the gpdat register without taking the shadow register into account,
thus accidentally setting other output gpios (at least those whose
value cannot be read back) to 0 at the same time.

When changing a gpio from input to output, we still need to make sure
it initially has the requested value. So, the procedure is

- update the shadow register
- compute the new gpdir register
- write the bitwise and of the shadow and new gpdir register to gpdat
- write the new gpdir register

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Rasmus Villemoes
1d7ad9fa05 gpio: mpc8xxx: don't modify gpdat when setting gpio as input
Since some chips don't support reading back the value of output gpios
from the gpdat register, we should not do a RMW cycle (i.e., the
clrbits_be32) on the gpdat register when setting a gpio as input, as
that might accidentally change the value of some other (still
configured as output) gpio.

The extra indirection through mpc8xxx_gpio_set_in() does not help
readability, so just fold the gpdir update into
mpc8xxx_gpio_direction_input().

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-03-31 10:06:52 -04:00
Tom Rini
9a8942b53d sandbox conversion to SDL2
TPM TEE driver
 Various minor sandbox video enhancements
 New driver model core utility functions
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Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
2020-02-11 10:58:41 -05:00
Fabio Estevam
c0a179a7a5 gpio: Let DM_74X164 be built without CONFIG_SPL_GPIO
Since commit bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
CONFIG_DM_74X164 is no longer built for mx7dsabresd_defconfig, as
this target does not use CONFIG_SPL_GPIO.

Remove such dependency and let the the 74X164 GPIO driver be built
again.

This restores Ethernet functionality on the imx7-sdb board as the
Ethernet reset PHY comes from a GPIO driven by a 74LV595PW I/O
expander.

Fixes: bcee8d6764 ("dm: gpio: Allow control of GPIO uclass in SPL")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Alifer Moraes <alifer.wsdm@gmail.com>
2020-02-09 14:52:39 +01:00
Jason Li
2ccacf3c7f gpio: cortina_gpio: add DM_GPIO driver for CAxxxx SoCs
DM_GPIO based GPIO controller driver for CAxxxx SoCs.
This driver support multiple CPU architectures and
Cortina Access SoC platforms.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Jason Li <jason.li@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
2020-02-07 14:01:21 -05:00
Simon Glass
336d4615f8 dm: core: Create a new header file for 'compat' features
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.

Move the compatibility features into a separate header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Simon Glass
61b29b8268 dm: core: Require users of devres to include the header
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-02-05 19:33:46 -07:00
Simon Glass
093152f275 gpio: Rename free() to rfree()
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-02-05 19:33:46 -07:00
Tom Rini
d4827fcd4c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Various minor fixes for x86
- Switch to ACPI mode on Intel edison
- Support run-time configuration for NS16550 driver
- Update coreboot and slimbootloader serial drivers to use NS16550
run-time configuration
- ICH SPI driver fixes to hardware sequencing erase case
- Move ITSS from Apollo Lake to a more generic location
- Intel GPIO driver bug fixes
- Move to vs2017-win2016 platform build host for Azure pipelines
2020-02-04 11:36:49 -05:00
Wolfgang Wallner
ea86e725d4 gpio: intel_gpio: Fix register/bit offsets intel_gpio_get_value()
Fix the following in intel_gpio_get_value():

 * The value of the register is contained in the variable 'reg', not in
   'mode'. The variable 'mode' contains only the configuration whether
   the gpio is currently an input or an output.

 * The correct bitmasks for the input and output value are
   PAD_CFG0_RX_STATE and PAD_CFG0_TX_STATE.
   Use them instead of the currently used PAD_CFG0_RX_STATE_BIT and
   PAD_CFG0_TX_STATE_BIT.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 12:54:55 +08:00
Wolfgang Wallner
28c626804d gpio: intel_gpio: Clear tx state bit when setting output
Add missing 'PAD_CFG0_TX_STATE' to the clear mask for pcr_clrsetbits32().
Otherwise this bit cannot be cleared again after it has been set once.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 12:54:55 +08:00
Wolfgang Wallner
b840c395c6 gpio: intel_gpio: Pass pinctrl device to pcr_clrsetbits32()
The function pcr_clrsetbits32() expects a device with a P2SB parent
device. In intel_gpio_direction_output() and intel_gpio_set_value()
the device 'dev' is passed to pcr_clrsetbits32(), which is a
gpio-controller with a device 'pinctrl' as parent. This does not match
the expectations of pcr_clrsetbits32(). But the 'pinctrl' device has a
P2SB as parent.

Pass the 'pinctrl' device instead of the 'dev' device to
pcr_clrsetbits32().

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 12:54:54 +08:00
Vignesh Raghavendra
25216d68fa gpio: da8xx_gpio: Add "ti,keystone-gpio" compatible
Add "ti,keystone-gpio" compatible so as be able to use Linux DT files as
is.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Vignesh Raghavendra
94f992d57a gpio: da8xx_gpio: Fix compiler warning
Fix below compiler warning for 64bit builds

drivers/gpio/da8xx_gpio.c: In function ‘davinci_get_gpio_bank’:
drivers/gpio/da8xx_gpio.c:446:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  return (struct davinci_gpio *)addr;

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Vignesh Raghavendra
dd6638a018 gpio: pca953x_gpio: Add support for 24 bit IO expander
J721e EVM has a TCA6424 IO expander that has 24 GPIOs. Add support for
the same

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Philippe Reynes
17f34ca803 gpio: bcm6345: allow to use this driver on arm bcm68360
This IP is also used on some arm SoC, so we allow to
use it on arm bcm68360 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-01-23 07:29:58 -05:00
Giulio Benetti
abd98e05a2 gpio: mxc_gpio: add support for i.MXRT1050
Add i.MXRT1050 support, there are 5 GPIO banks.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2020-01-14 22:53:59 +01:00
Simon Glass
7e589bc19b x86: Add a generic Intel GPIO driver
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
bcee8d6764 dm: gpio: Allow control of GPIO uclass in SPL
At present if CONFIG_SPL_GPIO_SUPPORT is enabled then the GPIO uclass
is included in SPL/TPL without any control for boards. Some boards may
want to disable this to reduce code size where GPIOs are not needed in
SPL or TPL.

Add a new Kconfig option to permit this. Default it to 'y' so that
existing boards work correctly.

Change existing uses of CONFIG_DM_GPIO to CONFIG_IS_ENABLED(DM_GPIO) to
preserve the current behaviour. Also update the 74x164 GPIO driver since
it cannot build with SPL.

This allows us to remove the hacks in config_uncmd_spl.h and
Makefile.uncmd_spl (eventually those files should be removed).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 08:52:29 +08:00
James Byrne
f3510e9754 gpio: at91_gpio: Add bank names
Make the at91_gpio driver set sensible GPIO bank names in the platform
data. This makes the 'gpio status' command a lot more useful.

Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-12-03 10:17:25 +02:00
Keerthy
3135022cb4 gpio: da8xx_gpio: Fix the _gpio_direction_output function
_gpio_direction_output function currently calls gpio_set_value
with the wrong gpio number. gpio_set_value in the uclass driver
expects a different gpio number and the _gpio_direction_output
is currently providing the number specific to the bank.

Hence fix it by calling the _gpio_set_value function instead.

Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci")
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-10-30 17:48:47 -04:00
Shubhrajyoti Datta
98927daada gpio: zynq: Add gpio driver support for PMC gpio
This patch adds support for gpio driver for pmc gpio.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Ashok Reddy Soma
982485214f gpio: zynq: Add gpio driver support for Versal
This patch adds support for gpio driver for versal platform

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Sagar Shrikant Kadam
d26b40450b gpio: sifive: add support for DM based gpio driver for FU540-SoC
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.

This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra <wesley@sifive.com> and/or Atish Patra
<atish.patra@wdc.com> (many thanks !!). The linux driver can be referred
here [1]

[1]: https://lkml.org/lkml/2018/10/9/1103

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-18 09:04:01 +08:00
Tom Rini
44fb0d6c9f Xilinx/FPGA changes for v2020.01
FPGA:
 - Enable fpga loading on Versal
 - Minor fix
 
 Microblaze:
 - Fix LMB configurations to support initrds
 - Some other cleanups
 
 Zynq:
 - Minor config/dt changes
 - Add distro boot support for usb1 and mmc1
 - Remove Xilinx private boot commands and use only distro boot
 
 ZynqMP:
 - Kconfig cleanups, defconfig updates
 - Update some dt files
 - Add firmware driver for talking to PMUFW
 - Extend distro boot support for jtag
 - Add new IDs
 - Add system controller configurations
 - Convert code to talk firmware via mailbox or SMCs
 
 Versal:
 - Add board_late_init()
 - Add run time DT memory setup
 - Add DFU support
 - Extend distro boot support for jtag and dfu
 - Add clock driver
 - Tune mini configurations
 
 Xilinx:
 - Improve documentation (boot scripts, dt binding)
 - Enable run time initrd_high calculation
 - Define default SYS_PROMPT
 - Add zynq/zynqmp virtual defconfig
 
 Drivers:
 - Add Xilinx mailbox driver for talking to firmware
 - Clean zynq_gem for Versal
 - Move ZYNQ_HISPD_BROKEN to Kconfig
 - Wire genphy_init() in phy.c
 - Add Xilinx gii2rgmii bridge
 - Cleanup zynq_sdhci
 - dwc3 fix
 - zynq_gpio fix
 - axi_emac fix
 
 Others:
 - apalis-tk1 - clean config file
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Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01

FPGA:
- Enable fpga loading on Versal
- Minor fix

Microblaze:
- Fix LMB configurations to support initrds
- Some other cleanups

Zynq:
- Minor config/dt changes
- Add distro boot support for usb1 and mmc1
- Remove Xilinx private boot commands and use only distro boot

ZynqMP:
- Kconfig cleanups, defconfig updates
- Update some dt files
- Add firmware driver for talking to PMUFW
- Extend distro boot support for jtag
- Add new IDs
- Add system controller configurations
- Convert code to talk firmware via mailbox or SMCs

Versal:
- Add board_late_init()
- Add run time DT memory setup
- Add DFU support
- Extend distro boot support for jtag and dfu
- Add clock driver
- Tune mini configurations

Xilinx:
- Improve documentation (boot scripts, dt binding)
- Enable run time initrd_high calculation
- Define default SYS_PROMPT
- Add zynq/zynqmp virtual defconfig

Drivers:
- Add Xilinx mailbox driver for talking to firmware
- Clean zynq_gem for Versal
- Move ZYNQ_HISPD_BROKEN to Kconfig
- Wire genphy_init() in phy.c
- Add Xilinx gii2rgmii bridge
- Cleanup zynq_sdhci
- dwc3 fix
- zynq_gpio fix
- axi_emac fix

Others:
- apalis-tk1 - clean config file
2019-10-09 16:22:03 -04:00
Tom Rini
eaa0bde051 u-boot-imx-20191009
-------------------
 
 Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532
 
 - MX6UL / ULZ
 - Toradex board
 - Allow to set OCRAM for MX6Q/D
 - MX7ULP
 - MX8: (container image, imx8mq_mek), SCU API
 - fix several board booting from SD/EMMC (cubox-i for example)
 - pico boards
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Merge tag 'u-boot-imx-20191009' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191009
-------------------

Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/595148532

- MX6UL / ULZ
- Toradex board
- Allow to set OCRAM for MX6Q/D
- MX7ULP
- MX8: (container image, imx8mq_mek), SCU API
- fix several board booting from SD/EMMC (cubox-i for example)
- pico boards

[trini: display5 merged manually]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-10-09 11:44:45 -04:00
Lukasz Majewski
c883d6a0f4 spi: Add support for SPL_OF_PLATDATA to mxs_gpio.c driver
After this patch the mxs_gpio.c DM/DTS driver can be used at early SPL to
read states of gpio pins (and for example alter the boot flow).

It was necessary to adjust its name to 'fsl_imx_2{38}_gpio' to match
requirements for SPL_OF_PLATDATA usage.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-08 16:36:36 +02:00
Ashok Reddy Soma
0384ac0583 gpio: zynq: fix issue in set gpio output direction
This patch fixes zynq_gpio_direction() to call driver specific
zynq_gpio_set_value function rather than top level gpio_set_value.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-08 09:53:04 +02:00
Simon Glass
27084c03d3 spl: Allow tiny printf() to be controlled in SPL and TPL
At present there is only one control for this and it is used for both SPL
and TPL. But SPL might have a lot more space than TPL so the extra cost of
a full printf() might be acceptable.

Split the option into two, providing separate SPL and TPL controls. The
TPL setting defaults to the same as SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:45 +08:00
Simon Glass
a605b0f767 sandbox: spmi: Add ranges property for address translation
At present address translation does not work since there is no ranges
property in the spmi nodes. Add empty ranges properties and a little more
logging so that this shows the error:

   /tmp/b/sandbox/u-boot -d /tmp/b/sandbox/arch/sandbox/dts/test.dtb \
	-c "ut dm spmi_access_peripheral" -L7 -v
   ...
   pm8916_gpio_probe() bad address: returning err=-22

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:39 +08:00
Lukasz Majewski
5484793363 kconfig: Convert CONFIG_MXS_GPIO to Kconfig
This converts the following to Kconfig:
   CONFIG_MXS_GPIO

Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/571260789

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-08-23 13:59:06 -04:00
Heiko Schocher
49b10cb492 gpio: fixes for gpio-hog support
recently added gpio hog patch was "in discussion"
state with Simon Glass. This patch now adds most
of comments from Simon Glass.

Signed-off-by: Heiko Schocher <hs@denx.de>
2019-07-29 09:32:10 -04:00
Lukasz Majewski
01941377ff gpio: Add missing parenthesis to the GPIO_TO_PORT define
Add missing parenthesis to the GPIO_TO_PORT macro.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-19 20:14:50 +02:00
Lukasz Majewski
397af35601 gpio: mxs: Add support for DM/DTS in the mxs_gpio.c driver (DM_GPIO)
This patch adds support for DM/DTS in the mxs_gpio.c driver.
Information regarding per gpio controller pin number is passed via DTS.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2019-07-19 14:57:14 +02:00
Tom Rini
0e80dda32c Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- Beelink-x2 STB support (Marcus)
- H6 DDR3, LPDDR3 changes (Andre, Jernej)
- H6 pin controller, USB PHY (Andre)
2019-07-16 11:19:31 -04:00
Andre Przywara
0d3c77f5c3 sunxi: gpio: Enable support for H6 pin controller
The Allwinner H6 pin controller is not really special, at least not when
it comes to normal GPIO operation.

Add the H6 compatible strings to the list of recognised strings, to make
GPIOs work for H6 boards.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:13:15 +05:30
Andre Przywara
10cfbaabc1 sunxi: move SUNXI_GPIO to Kconfig
Probably for no particular reason SUNXI_GPIO was still defined the "old
way", in header files only.

Introduce SUNXI_GPIO to the Kconfig file in drivers/gpio to remove
another line from our dreadful config_whitelist.txt.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-16 17:13:15 +05:30
Tom Rini
a9a3a37f92 - syscon: add support for power off
- stm32mp1: add op-tee config
 - stm32mp1: add specific commands: stboard and stm32key
 - add stm32 mailbox driver
 - solve many stm32 warnings when building with W=1
 - update stm32 gpio driver
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Merge tag 'u-boot-stm32-20190712' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- syscon: add support for power off
- stm32mp1: add op-tee config
- stm32mp1: add specific commands: stboard and stm32key
- add stm32 mailbox driver
- solve many stm32 warnings when building with W=1
- update stm32 gpio driver
2019-07-14 09:09:49 -04:00
Heiko Schocher
5fc7cf8c8e gpio: add gpio-hog support
add gpio-hog support. GPIO hogging is a mechanism
providing automatic GPIO request and configuration
as part of the gpio-controller's driver probe function.

for more infos see:
doc/device-tree-bindings/gpio/gpio.txt

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Michal Simek <michal.simek@xilinx.com> (zcu102)
Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-13 11:11:30 -04:00
Patrice Chotard
60bc487666 gpio: stm32: Remove .ofmatch callback
As compatible string "st,stm32-gpio" is no more used, .ofmatch
callback becomes useless, remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:58 +02:00
Patrice Chotard
95fbdd1ad8 gpio: stm32: Rename stm32f7_gpio to stm32_gpio
As this driver is used on stm32f4/f7/h7 and stm32mp1
SoCs, rename it with a more generic name.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:58 +02:00
Patrick Delaunay
99e14b2793 gpio: stm32_gpio: Fix warnings when compiling with W=1
This patch solves the following warnings:

drivers/gpio/stm32_gpio.c: In function 'stm32_offset_to_index':
: comparison between signed and unsigned integer expressions [-Wsign-compare]
    if (idx == offset)
            ^~
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-07-12 11:50:55 +02:00
Marek Vasut
4a09831ab2 gpio: pca953x: Add TI TCA9539 compatible string
Add TI TCA9539 compatible string for yet another I2C GPIO expander.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-07-11 14:11:20 -04:00
Simon Goldschmidt
34b1a510e8 gpio: dwapb_gpio: fix broken dev->node
commit 1b898ffc04 ("gpio: dwapb_gpio: convert to livetree") introduced
a bug in that dev->node of the gpio chip was accidentally set to the
of_node of its bank subnode.

What it meant to do was assign subdev->node, not dev->node.

While this doesn't affect too many use cases, iterating over the gpio
chip's properties doesn't work any more after that, so fix this.

Fixes: commit 1b898ffc04 ("gpio: dwapb_gpio: convert to livetree")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-24 00:01:08 +02:00
Simon Goldschmidt
1b898ffc04 gpio: dwapb_gpio: convert to livetree
Convert 'gpio_dwapb_bind' to iterate over subnodes using livetree
functions (inspired from mt7621_gpio.c).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10 22:48:11 +02:00
Marek Vasut
86b8e7d61a gpio: renesas: Add RZ/A1 R7S72100 GPIO driver
Add GPIO driver for RZ/A1 SoC. The IP is very different from the
R-Car Gen2/Gen3 one already present in the tree, hence a custom
driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-07 05:41:32 +02:00
Tom Rini
44237e272f Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various pinctrl / gpio fixes for R-Car
2019-05-06 07:19:31 -04:00
Tom Rini
86f578ee85 - mscc: small fixes, enhance network support for Serval, Luton amd
Ocelot
 - mt7620: rename arch to more generic name mtmips
 - mips: pass initrd addresses via DT as physical addresses
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Merge tag 'mips-pull-2019-05-03' of git://git.denx.de/u-boot-mips

- mscc: small fixes, enhance network support for Serval, Luton and Ocelot
- mt7620: rename arch to more generic name mtmips
- mips: pass initrd addresses via DT as physical addresses
2019-05-04 20:02:42 -04:00
Marek Vasut
fbf26bea39 gpio: renesas: Migrate to pinctrl GPIO accessors
Switch to generic pin controller API for configuring pins as GPIOs
instead of using the ad-hoc call into the R-Car PFC driver. Moreover,
add .free() implementation for the GPIO controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Christoph Muellner <christoph.muellner@theobroma-systems.com>
Cc: Eugeniu Rosca <roscaeugeniu@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Simon Glass <sjg@chromium.org>
2019-05-04 19:26:49 +02:00
Weijie Gao
16b94903e2 mips: rename mach-mt7620 to mach-mtmips
Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
because they do not share the same lowlevel codes.

Dependencies of four drivers are changed to SOC_MT7628 as these drivers
are only used by MT7628.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-05-03 16:43:11 +02:00
Kever Yang
15f09a1a83 rockchip: use 'arch-rockchip' as header file path
Rockchip use 'arch-rockchip' instead of arch-$(SOC) as common
header file path, so that we can get the correct path directly.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-01 00:00:05 +02:00
Philippe Reynes
353496b756 gpio: bcm6345: allow this driver on ARCH_BCM63158
This IP is also used on some arm SoC, so we allow
to use this driver on arch bcm63158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
14c9bd46e5 gpio: bcm6345: allow this driver on ARCH_BCM6858
This IP is also used on some arm SoC, so we allow
to use this driver on arch bcm6858.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-12 17:32:51 +02:00
Philippe Reynes
ea0d6aa213 gpio: bcm6345: switch to raw I/O functions
This driver is used on several big endian mips board.
So we could use raw I/O function instead of forcing
big endian access.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-12 17:32:51 +02:00
Julien Béraud
97b262758b gpio: altera_pio: fix get_value
gpio_get_value should return 0 or 1, not the value of bit & (1 << pin)

Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
2019-02-25 16:07:36 +01:00
Simon Glass
aa48c94ca8 rockchip: Implement spl_gpio in the GPIO driver
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Peng Fan
1610368234 gpio: introduce CONFIG_SPL_DM_PCA953X
Introduce CONFIG_SPL_DM_PCA953X for SPL usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Lars Povlsen
ace9c103df mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-01-16 13:56:43 +01:00
Lars Povlsen
be8313feee mips: mscc_sgpio: Add the MSCC serial GPIO device (SIO)
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.

By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.

This adds the base driver.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-01-16 13:56:43 +01:00
Patrice Chotard
4fb224638d gpio: stm32f7: Fix SPL code size
In order to keep SPL code size below the 32Kb limit,
put under CONFIG_SPL_BUILD flag all unused code in SPL.
This is needed for stm32f7xx board which are using SPL.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-01-09 07:13:33 -05:00
Patrice Chotard
39a8f0be2d gpio: stm32f7: Fix gpio bank hole management
In case "gpio-ranges" property is not present in device tree,
use default value for gpio_count and gpio_range.
This fixes an issue on stm32 F7 and H7 boards where "pinmux status -a"
command didn't return any pin status due to the fact that both stm32 F7
and H7 board DT doesn't use the gpio-ranges property.

Fixes: dbf928dd2634a6("gpio: stm32f7: Add gpio bank holes management")

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-01-09 07:13:32 -05:00
Tom Rini
522e035441 imx for 2019.01
- introduce support for i.MX8M
 - fix size limit for Vhybrid / pico boards
 - several board fixes
 - w1 driver for MX2x / MX5x
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Merge tag 'u-boot-imx-20190101' of git://www.denx.de/git/u-boot-imx

imx for 2019.01

- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x
2019-01-01 10:01:00 -05:00
Peng Fan
cd357ad112 imx: rename mx8m,MX8M to imx8m,IMX8M
Rename mx8m,MX8M to imx8m,IMX8M

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
2019-01-01 14:12:18 +01:00
Gregory CLEMENT
02aea4da1d gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.

Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.

Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Patrice Chotard
8b6d45ab64 gpio: stm32f7: Remove CONFIG_CLK flag.
As all STM32 SoCs supports CONFIG_CLK flag,
it becomes useless in this driver, remove it.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:48 -05:00
Patrice Chotard
b2f84e37e2 gpio: stm32f7: Move STM32_GPIOS_PER_BANK into gpio.h
To allow access to this define by other driver, move
it into gpio.h

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Patrice Chotard
dbf928dd26 gpio: stm32f7: Add gpio bank holes management
In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.

For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-12-07 08:13:47 -05:00
Simon Goldschmidt
89f1fe5bd4 gpio: dwapb_gpio: fix binding without bank-name property
As a preparation for merging the socfpga gen5 devicetree files
from Linux, this patch makes the dwapb gpio driver work correctly
without the 'bank-name' property on the gpio-controller nodes.

This property is not present in the Linux drivers and thus is not
present in the Linux devicetrees. It is only used to access pins
via bank name.

This fallback is necessary since without it, the driver will
return an error code which will lead to an error in U-Boot
startup.

The bank names will still be added to the default board device
trees in follow-up patch, but other boards using this driver and
not including the bank name should also work with the socfpga.dtsi
without adding the bank-name property.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2018-11-29 12:45:15 +01:00
Stefan Roese
4751e5595e gpio: Add MT7621 GPIO support
This patch adds GPIO support for the Mediatek MT7621 SoC, tested on
MT7688 (Gardena smart-gateway). The driver is loosly based on the
Linux kernel version.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[fixed checkpatch.pl warnings: Prefer 'unsigned int' to bare use of 'unsigned']
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Patrice Chotard
cad732499b gpio: stm32f7: Add ops get_function
This patch adds gpio get_function ops support.
This function reports the state of a gpio.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-11-16 16:51:56 -05:00
Ye Li
3764b2bdce gpio: pca953x: Clear the polarity invert register at init
The pca953x_gpio driver uses default value of polarity inversion
register. For some devices like PCA9557 and MAX7310, their polarity
inversion register default value is 0xf0. So for high 4 ports, when
reading their values, the values are inverted as the actual level.

This patch clears the polarity inversion register to 0 at init, so
that the port read and write values are aligned.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2018-11-16 13:34:36 -05:00
Bin Meng
695c4994ac gpio: Remove DM_FLAG_PRE_RELOC flag in various drivers
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.

To mitigate this potential impact, the following changes are
implemented:

- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
  only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
  is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
  drivers that support both statically declared devices and
  configuration from device tree

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-11-14 09:16:28 -08:00
Anatolij Gustschin
745915aa59 gpio: pca953x_gpio: fix DT GPIO flags translation
Commit fb01e07a95 accidentally broke initialisation of GPIO
descriptor flags from device tree: currently the active low
flag from gpio-specifier is always ignored. Fix it.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Mario Six <mario.six@gdsys.cc>
2018-11-14 10:59:23 -05:00
Tom Rini
cf033e04da Merged imx8 architecture, fix build for imx8 + warnings
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Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx

Merged imx8 architecture, fix build for imx8 + warnings
2018-10-25 10:16:21 -04:00
Peng Fan
8b2a31f133 gpio: mxc_gpio: add support for i.MX8
Add i.MX8 support, there are 8 GPIO banks.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2018-10-22 12:59:01 +02:00
Keerthy
0f3cf2b3e5 gpio: da8xx: Push generic defines of gpio.h out of mach-davinci
Push generic defines of gpio.h out of mach-davinci to drivers/gpio
now that non-davinci architectures are beginning to use this IP.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Fix calimain build]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-10 13:35:03 -04:00
Keerthy
401d74cb2c gpio: da8xx: Add k2g compatible
Add k2g compatible so that k3 SoCs can be supported

Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-10-10 13:32:41 -04:00
Ley Foon Tan
86d56a5da5 gpio: dwapb_gpio: Change to use devm_kcalloc()
Change to use managed resource function devm_kcalloc(),
so it will auto free memory when driver is removed.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-10-03 12:56:50 +02:00
Ley Foon Tan
9ea354444d gpio: dwapb_gpio: Change to use dev_read_addr()
This changes the driver to use dev_read_addr() which is safe both for
flat trees and live trees.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-09-15 03:17:01 +02:00
Ley Foon Tan
db6a158bc3 gpio: dwapb_gpio: Add reset ctrl to driver
Add code to reset all reset signals as in gpio DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.

If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-09-15 03:17:01 +02:00
Ley Foon Tan
71f2700b92 gpio: dwapb_gpio: Enable get_function support
Enabled get_function support for dwapb where the function will
return the state of GPIO port.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-09-15 03:17:01 +02:00
Adam Ford
99571b41c6 DM: omap_gpio: Reduce overhead when used with OF_PLATDATA
Platforms with limited resources in SPL may enable OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree.  This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-09-11 21:38:52 -04:00
Adam Ford
535f46dad9 GPIO: omap_gpio: Fix gpio name names with device tree
The GPIO bank numbers do not appear in the device tree, so this
patch makes the gpio name based on the address
(ie gpio@49054000_31 vs gpio4_31)

adam

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Derald D. Woods <woods.technical@gmail.com>
2018-09-11 21:38:15 -04:00
Adam Ford
9440b3d3d0 dm: gpio: da8xx_gpio: Add support for GPIO_ACTIVE_LOW/HIGH
With DM and device tree support, let's use the GPIO_ACTIVE_HIGH
and GPIO_ACTIVE_LOW from the device tree as they are intended.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-11 21:38:00 -04:00
Adam Ford
1eddf54931 DM: GPIO: Fix da8xx GPIO indexing over GPIO 32
The GPIO banks are broken up into two 16-bit registers for each
bank set.  Unfortunately, the math that determines how to shift
blindly shifted by the number of the gpio.  This worked for gpio
numbers under 32, but higher gpio's are broken.  This fixes the
gpio index, so the bank is passed and the shift amount within
the register is passed now instead of the gpio number.

Fixes: 8e51c0f25406("dm: gpio: Add DM compatibility to
GPIO driver for Davinci")

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-09-11 21:37:50 -04:00
Patrice Chotard
798cd708d5 gpio: stm32f7: replace ODR update by BSRR write
Replace clrsetbits on ODR register (2 operations: one read + one write)
by writing on the correct bit (SET or RESET) of the BSRR register
(only 1 write operation).

Moreover this register if safe for simultaneous access by 2 master on
the bus.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-09-10 20:48:18 -04:00
Michal Simek
312dd1c55c gpio: xilinx: Add support for using label property
Add support for reading label property from DT and set up bank name
based on that. If label property is not present full device node name is
used.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
2018-08-07 11:03:43 +02:00
Michal Simek
ac7f061398 gpio: xilinx: Return 0 from xilinx_gpio_set_value
.set_value functions have no specified return value and gpio_uclass is
not working with it too. But this patch is returning 0 to be in sync
with others DM gpio drivers.

Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
2018-08-07 11:03:43 +02:00
Michal Simek
c714aeaec1 gpio: xilinx: Not read output values via regs
Reading registers for finding out output value is not working because
input value is read instead in case of tristate.

Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
2018-08-07 11:03:43 +02:00
Michal Simek
642a860412 gpio: xilinx: Simplify logic in xilinx_gpio_set_value
There is no reason to do read/write for if/else separately.

Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
2018-08-07 11:03:43 +02:00
Michal Simek
bf2a69de81 gpio: xilinx: Set value before changing direction
Set a value before changing gpio direction. This will ensure that the
old value is not propagated when direction has changed but new value is
not written yet.

Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
2018-08-07 11:03:43 +02:00
Michal Simek
6f81ff0422 gpio: xilinx: Remove !DM driver
There is no user for !DM driver that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-07 11:03:43 +02:00
Michal Simek
ddd7b3fa33 gpio: xilinx: Find out bank before use in xilinx_gpio_get_function()
Call xilinx_gpio_get_bank_pin() before use.

Reported-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
2018-08-07 11:03:42 +02:00
Vipul Kumar
0f07257345 gpio: zynq: Used platdata structure for storing static data instead of priv
This patch used platdata structure instead of priv for storing static
information read from DT.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-08-06 08:44:35 +02:00
Eugeniy Paltsev
fe3eb7a887 GPIO: CREG: improve flexibility of hsdk-creg-gpio driver
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.

Example:

31                 9        7        5           0   < bit number
|                  |        |        |           |
[     not used     | gpio-1 | gpio-0 | <-shift-> ]   < 32 bit register
                       ^        ^
                       |        |
                write 0x2 == set output to "1" (activate)
                write 0x3 == set output to "0" (deactivate)

As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.

Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-07-31 07:49:47 +03:00
Adam Ford
5d653afc17 Convert CONFIG_DA8XX_GPIO to Kconfig
This converts the following to Kconfig:
   CONFIG_DA8XX_GPIO

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-07-23 14:33:21 -04:00
Michal Simek
4a69366967 microblaze: Convert generic platform to DM gpio
Converting GPIO to DM requires to do changes in reset subsystem
that's why support for Microblaze soft reset via sysreset and GPIO
sysreset support was added.
These two patches enables enabling GPIO DM.
Microblaze soft reset is bind at last reset method.

GPIO reset is handled via sysreset with adding this fragment to DT.

gpio-restart {
	compatible = "gpio-restart";
	gpios = <&reset_gpio 0 0 0>;
	/* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */
};

hard-reset-gpio property is not documented and also handled.
Conversion is required.

Unfortunately do_reset is required for SPL that's why use only soft
microblaze reset for now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-07-19 10:49:55 +02:00