Commit graph

10 commits

Author SHA1 Message Date
York Sun
1478fdef52 armv8/fsl-lsch3: Enable erratum workround for A008514
Erratum A008514 appleis to ls2085a.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:12 -08:00
York Sun
a5ebdf06a0 armv8/fsl-lsch3: Enable workaround for A008336
Erratum A008336 applied to LS2085A.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:10:08 -08:00
York Sun
b87e6f88e9 armv8/fsl-lsch3: Add support for second DDR clock
FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for
general DDR controlers, and another clock for DP-DDR. DDR driver needs to
change to support multiple clocks.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:14 -08:00
York Sun
9955b4ab01 driver/ddr/fsl: Add workaround for A008336
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:06 -08:00
Bhupesh Sharma
9c66ce662c fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses
This patch ensures that the TZPC (BP147) and TZASC-400 programming
happens for LS2085A SoC only when the desired config flags are
enabled and ensures that the TZPC programming is done to allow Non-secure
(NS) + secure (S) transactions only for DCGF registers.

The TZASC component is not present on LS2085A-Rev1, so the TZASC-400
config flag is turned OFF for now.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:06 -08:00
York Sun
40f8dec54d armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page
Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-25 08:36:19 -07:00
York Sun
d9c68b1444 ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory block
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
York Sun
f749db3a75 ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support
LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2014-07-04 19:48:41 +02:00
York Sun
2f78eae506 ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-07-03 08:40:51 +02:00