Commit graph

11 commits

Author SHA1 Message Date
Stefano Babic
69df00f9d9 ARM: add accessors functions
Some Freescale's processors of different architecture
have the same peripheral (eSDHC controller in PowerPC
and i.MX51). This patch adds accessors for
the internal registers of the SOCs, as already
implemented in the PowerPC architecture.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-03-07 12:36:36 -06:00
Kumar Gala
65e43a1063 Introduce virt_to_phys()
virt_to_phys() returns the physical address given a virtual. In most
cases this will be just the input value as the vast majority of
systems run in a 1:1 mode.

However in systems that are not running this way it should report the
physical address or ~0 if no mapping exists for the given virtual
address.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-12-15 22:04:29 +01:00
Marcel Ziswiler
6fdd002689 Fix misspelled comment
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2008-05-04 00:01:08 +02:00
Kumar Gala
e99ccb4881 Introduce phys_size_t and move phys_addr_t into asm/types.h
Also add CONFIG_PHYS_64BIT on powerpc to deal with 32-bit ppc's
that have larger physical addresses like 44x, 85xx, and 86xx.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-04-13 17:13:46 -07:00
Haavard Skinnemoen
4d7d6936eb Introduce map_physmem() and unmap_physmem()
map_physmem() returns a virtual address which can be used to access a
given physical address without involving the cache. unmap_physmem()
should be called when the virtual address returned by map_physmem() is
no longer needed.

This patch adds a stub implementation which simply returns the
physical address cast to a uchar * for all architectures except AVR32,
which converts the physical address to an uncached virtual mapping.
unmap_physmem() is a no-op on all architectures, but if any
architecture needs to do such mappings through the TLB, this is the
hook where those TLB entries can be invalidated.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
2007-12-13 13:15:16 +01:00
Haiying Wang
3a197b2fe4 [PATCH v3] Add sync to ensure flash_write_cmd is fully finished
Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command
is fully finished. The sync() is defined in each CPU's io.h file. For
those CPUs which do not need sync for now, a dummy sync() is defined in
their io.h as well.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2007-02-21 16:52:31 +01:00
Wolfgang Denk
ac7eb8a315 Update of new NAND code
Patch by Ladislav Michl, 13 Sep 2005
2005-09-14 23:53:32 +02:00
wdenk
8ed9604613 * Patches by Richard Woodruff, 01 Oct 2004:
add support for the TI OMAP2420 processor and its H4 reference
  board

* Patch by Christian Pellegrin, 24 Sep 2004:
  Added support for NE2000 compatible (DP8390, DP83902) NICs.
2005-01-09 23:16:25 +00:00
wdenk
b783edaee8 * Header file cleanup for ARM
* Patch by Murray Jensen, 24 Jun 2003:
  - make sure to use only U-boot provided header files
  - fix problems with ".rodata.str1.4" section as used by GCC-3.x
2003-06-25 22:26:29 +00:00
wdenk
06d01dbe00 * Avoid flicker on the TRAB's VFD by synchronizing the enable with
the HSYNC/VSYNC. Requires new CPLD code (Version 101 for Rev. 100
  boards, version 153 for Rev. 200 boards).

* Patch by Vladimir Gurevich, 12 Mar 2003:
  Fix relocation problem of statically initialized string pointers
  in common/cmd_pci.c

* Patch by Kai-Uwe Blöm, 12 Mar 2003:
  Cleanup & bug fixes for JFFS2 code:
  - the memory mangement was broken. It caused havoc on malloc by
    writing beyond the block boundaries.
  - the length calculation for files was wrong, sometimes resulting
    in short file reads.
  - data copying now optionally takes fragment version numbers into
    account, to avoid copying from older data.
  See doc/README.JFFS2 for details.
2003-03-14 20:47:52 +00:00
wdenk
041b1deace Initial revision 2002-09-07 21:30:09 +00:00