Commit graph

15521 commits

Author SHA1 Message Date
Paul Gortmaker
7e44f2b710 sbc8548: Make enabling SPD RAM configuration work
Previously, SPD configuration of RAM was non functional on
this board.  Now that the root cause is known (an i2c address
conflict), there is a simple end-user workaround - remove the
old slower local bus 128MB module and then SPD detection on the
main DDR2 memory module works fine.

We make the enablement of the LBC SDRAM support conditional on
being not SPD enabled.  We can revisit this dependency as the
hardware workaround becomes available.

Turning off LBC SDRAM support revealed a couple implict dependencies
in the tlb/law code that always expected an LBC SDRAM address.

This has been tested with the default 256MB module, a 512MB
a 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration
worked fine in all cases.

The default configuration remains to go with the hard coded
DDR config, so the default build will continue to work on boards
where people don't bother to read the docs.  But the advantage
of going to the SPD config is that even the small default module
gets configured for CL3 instead of CL4.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:59:07 -06:00
Paul Gortmaker
5f4c6f0db9 sbc8548: Fix LBC SDRAM initialization settings
These were cloned from the mpc8548cds platform which has
a different memory layout (1/2 the size).  Set the values
by comparing to the register file for the board used during
JTAG init sequence:

	LSDMR1		0x2863B727	/* PCHALL */
	LSDMR2		0x0863B727	/* NORMAL */
	LSDMR3		0x1863B727	/* MRW    */
	LSDMR4		0x4063B727	/* RFEN   */

This differs from what was there already in that the RFEN is
not bundled in all four steps implicitly, but issued once
as the final step.

The other difference seen when comparing vs. the register file init,
is that since the memory is split across /CS3 and /CS4, the dummy
writes need to go to 0xf000_0000 _and_ to 0xf400_0000.

We also rewrite the final LBC SDRAM inits as macros, as there is
no real need for them to be a local variable that is modified
on the fly at runtime.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:59:03 -06:00
Paul Gortmaker
f0aec4ea33 sbc8548: enable ability to boot from alternate flash
This board has an 8MB soldered on flash, and a 64MB SODIMM
flash module.  Normally the board boots from the 8MB flash,
but the hardware can be configured for booting from the 64MB
flash as well by swapping CS0 and CS6.  This can be handy
for recovery purposes, or for supporting u-boot and VxBoot
at the same time.

To support this in u-boot, we need to have different BR0/OR0
and BR6/OR6 settings in place for when the board is configured
in this way, and a different TEXT_BASE needs to be used due
to the larger sector size of the 64MB flash module.

We introduce the suffix _8M and _64M for the BR0/BR6 and the
OR0/OR6 values so it is clear which is being used to map what
specific device.

The larger sector size (512k) of the alternate flash needs
a larger malloc pool, otherwise you'll get failures when
running saveenv, so bump it up accordingly.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:58:14 -06:00
Paul Gortmaker
3fd673cf36 sbc8548: relocate 64MB user flash to sane boundary
The current situation has the 64MB user flash at an awkward
alignment; shifted back from 0xfc00_0000 by 8M, to leave an 8MB hole
for the soldered on boot flash @ EOM.  But to switch to optionally
supporting booting off the 64MB flash, the 64MB will then be mapped
at the sane address of 0xfc00_0000.

This leads to awkward things when programming the 64MB flash prior
to transitioning to it -- i.e. even though the chip spans from
0xfb80_0000 to 0xff7f_ffff, you would have to program a u-boot image
into the two sectors from 0xfbf0_0000 --> 0xfbff_ffff so that it was
in the right place when JP12/SW2.8 were switched to make the 64MB on
/CS0. (i.e. the chip is only looking at the bits in mask 0x3ff_ffff)

We also have to have three TLB entries responsible for dealing with
mapping the 64MB flash due to this 8MB of misalignment.

In the end, there is address space from 0xec00_0000 to 0xefff_ffff
where we can map it, and then the transition from booting from one
config to the other will be a simple 0xec --> 0xfc mapping.  Plus we
can toss out a TLB entry.

Note that TLB0 is kept at 64MB and not shrunk down to the 8MB boot
flash; this means we won't have to change it when the alternate
config uses the full 64MB for booting, in TLB0.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:58:10 -06:00
Paul Gortmaker
af35be6ac9 Revert "SBC8548: fix address mask to allow 64M flash"
This reverts commit ccf1ad535a.

The commit "SBC8548: fix address mask to allow 64M flash"
essentially made this change:

  * OR6:
- *    Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0
+ *    Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0

But this makes no sense, as section 13.3.1.2.1 in the
MPC8548ERM v2 clearly indicates the masks:

	1111_1111_1000_0000_0	8 Mbytes
	1111_1100_0000_0000_0	64 Mbytes
	1111_1000_0000_0000_0	128 Mbytes

So the original value was correct, and the commit was invalid,
causing a 128MB mapping for a 64MB flash device.  The problem
rears its head when trying to configure u-boot to have access
to both flash, since the default memory map is:

	FB80_0000 – FF7F_FFFF 32-bits 64MB FLASH SODIMM
	FF80_0000 – FFFF_FFFF 8-bits 8MB FLASH

By extending the mapping of the 64MB flash to 128MB, it now
conflicts with the normal 8MB boot flash, causing issues.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:58:07 -06:00
Paul Gortmaker
1667013ddf MPC85xxCDS: Fix missing LCRR_DBYP bits for 66-133MHz LBC
These boards were meaning to deploy this value:

  #define LCRR_DBYP        0x80000000

but were missing a zero, and hence toggling a bit that
lands in an area marked as reserved in the 8548 reference
manual.

According to the documentation, LCRR_DBYP should be used as:

   PLL bypass. This bit should be set when using low bus
   clock frequencies if the PLL is unable to lock.  When in
   PLL bypass mode, incoming data is captured in the middle
   of the bus clock cycle.  It is recommended that PLL bypass
   mode be used at frequencies of 83 MHz or less.

So the impact would most likely be undefined behaviour for
LBC peripherals on boards that were running below 83MHz LBC.
Looking at the actual u-boot code, the missing DBYP bit was
meant to be deployed as follows:

      Between 66 and 133, the DLL is enabled with an
      override workaround.

In the future, we'll convert all boards to use the symbolic
DBYP constant to avoid these "count the zeros" problems, but
for now, just fix the impacted boards.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:57:56 -06:00
Kyle Moffett
0ecb55132b eXMeritus HWW-1U-1A: Add support for the AT24C128N I2C EEPROM
This EEPROM is hardware-write-protected and used to persist key
information such as the serial number and MAC addresses even if the
primary environment sector in NOR FLASH is overwritten.

During manufacturing, the environment is initialized from Linux and then
the key parameters copied to the EEPROM via U-Boot:

  env export -c -s 0x2000 $loadaddr serial# macaddr mac1addr mac2addr
  eeprom write $loadaddr 0x0000 0x2000

The chip is then locked via hardware for delivery.

When doing a field U-Boot upgrade, the environment is erased and reset
to the defaults to avoid problems with "hwconfig" changes, etc.  After
loading the new U-Boot image, the hardware data is reloaded:

  i2c dev 0
  eeprom read $loadaddr 0x0000 0x2000
  env import -c $loadaddr 0x2000
  saveenv

The first three commands are saved in the "restore_eeprom" variable for
user convenience.  (EG: "run restore_eeprom && saveenv")

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:57:53 -06:00
Kyle Moffett
7985f7e3ff eXMeritus HWW-1U-1A: Minor environment variable tweaks
Most of the ethernet connections are internal links with specialized
hardware and are not useful for "dhcp" or general-purpose networking;
U-Boot should not be cycling through them.  Force the primary external
network interface in "ethprime" and disable the interface cycling with
"ethrotate=no".

Additionally, the environment variable "preboot" has its own config
option and means something entirely different from what the HWW-1U-1A
variable was intended for.  Rename the board variable to "setbootargs"
to avoid potential confusion.

Finally, fix an incorrect address for the kernel in FLASH memory.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-01-11 13:57:51 -06:00
esw@bus-elektronik.de
781322755f fix: error ATMEL_FIO_BASE undeclared, if use I2C_Soft on AT91
* Since AT91 name schema was changed to ATMEL_BASE_xxx, I2C_SOFT
  on AT91 devices fails with 'error: ATMEL_FIO_BASE undeclared'
* change ATMEL_PIO_BASE to ATMEL_BASE_PIOA will fix this

Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
2012-01-11 08:03:46 +01:00
Scott Wood
c947c12e78 mpc8313erdb: fix mtdparts address
Fix a copy-and-paste error when adapting mpc8315erdb mtdparts
to mpc8313erdb.  mtdids was already using the proper address
on mpc8313erdb.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:34 -06:00
Holger Brunck
f5a474bd7a powerpc/83xx/km: add support for 8321 based tuge1 board
This board is similar to our tuxx1 target. But on this board there
is only one application specific chip select configured.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:34 -06:00
Holger Brunck
5f2a44d5ea powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
These boards are from a u-boot point of view identical. So collect
the two headerfiles to one, to decrease maintenance.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Holger Brunck
d926d186d7 powerpc/83xx/km: remove obsolete defines for tuda1
CONFIG_SYS_LCRR is unused and CONFIG_SYS_LBC_LBCR is already
defined in the common header file, so remove them.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Marco Schmid
513e396b4f powerpc/83xx/km: update SDRAM parameters for km8321 boards
Measurements during HW basic test showed, that the SDRAM timing
has to be optimized. This patch adapted these timings accordingly.

Signed-off-by: Marco Schmid <marco.schmid@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Joe Hershberger
0eaf8f9ea8 mpc8313erdb: Enable GPIO support on the MPC8313E RDB
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Joe Hershberger
4b56579388 mpc83xx: Add a GPIO driver for the MPC83XX family
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:33 -06:00
Joe Hershberger
365d607033 gpio: Replace ARM gpio.h with the common API in include/asm-generic
ARM boards should use the generic GPIO API
This means changing gpio to unsigned type
Remove the unused gpio_toggle() function which is not part of the API
Comment that free should not modify pin state

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>

fixed merge conflict in da8xx_gpio.c, tegra2_gpio.c, and
extended to the new mxs_gpio.c.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2012-01-09 20:10:32 -06:00
Joe Hershberger
5f533aeb51 gpio: Modify common gpio.h to more closely match Linux
Change "int gp" to "unsigned gpio"
Add request and free entry-points

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2012-01-09 20:10:32 -06:00
David Müller
d49f5b1cae board/mpl/pati: use the CFI driver for the PATI board
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-01-09 09:25:07 +01:00
David Müller
39441b35c6 board/mpl/mip405: use the CFI driver for the MIP405/MIP405T board
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-01-09 09:25:01 +01:00
David Müller
21be309bb7 board/mpl/pip405: use the CFI driver for the PIP405 board
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-01-09 09:24:56 +01:00
David Müller
4b11dba975 board/mpl/common: remove the old legacy flash
Signed-off-by: David Mueller <d.mueller@elsoft.ch>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-01-09 09:24:51 +01:00
Dirk Eibach
06b174124e ppc4xx: Setup HICB on Io64
The FPGA High-Speed Interconnect Bus (HICB) is now setup by u-boot.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-01-09 09:19:47 +01:00
Ira Snyder
8eee2bd7f4 fsl_esdhc: fix PIO mode transfers
The pointer to the registers used to control the Freescale ESDHC MMC
controller is not initialized correctly when using PIO mode. This is
fixed by initializing the pointer in the same way as all other sites
within the driver.

Examining the commit history shows that this was broken at introduction
due to a code change in upstream U-Boot to support the mx51 processor
family.

Reported-by: Jim Lentz <JLentz@zhone.com>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
2012-01-08 21:28:28 -06:00
Thierry Reding
bf83662ba3 mmc: tegra2: Implement card-detect hook.
On Tegra2, card-detection is implemented by passing the card-detection
GPIOs to the MMC driver at initialization time. Instead of implementing
the board_mmc_getcd() function, use the card-detect hook and allow
boards to override it by providing their own board_mmc_getcd()
implementation.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2012-01-08 21:28:28 -06:00
Thierry Reding
d48d2e21d4 mmc: fsl_esdhc: Implement card-detect hook.
This card-detect hook probably doesn't work. Perhaps somebody with more
knowledge about the hardware can comment on this. I think that perhaps
even the complete code from esdhc_init() could go into the getcd()
function instead or mmc_getcd() needs to be called at some later time
after mmc_init(), which, however, would require many other drivers to
change.

In addition to implementing the hook, this patch also removes the call
to the board_mmc_getcd() function which is now called from the MMC
framework and is no longer required here.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-01-08 21:28:28 -06:00
Thierry Reding
48972d907a mmc: Implement card detection.
Check for card detect each time an MMC/SD device is initialized. If card
detection is not implemented, this code behaves as before and continues
assuming a card is present. If no card is detected, has_init is reset
for the MMC/SD device (to force initialization next time) and an error
is returned.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-01-08 21:28:27 -06:00
Thierry Reding
314284b156 mmc: Change board_mmc_getcd() function prototype.
The new API no longer uses the extra cd parameter that was used to store
the card presence state. Instead, this information is returned via the
function's return value. board_mmc_getcd() returns -1 to indicate that
no card-detection mechanism is implemented; 0 indicates that no card is
present and 1 is returned if it was detected that a card is present.

The rationale for this change can be found in the following email
thread:

	http://lists.denx.de/pipermail/u-boot/2011-November/110180.html

In summary, the old API was not consistent with the rest of the MMC API
which always passes a struct mmc as the first parameter. Furthermore the
cd parameter was used to mean "card absence" in some implementations and
"card presence" in others.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Jason Liu <jason.hui@linaro.org>
2012-01-08 21:28:27 -06:00
Anatolij Gustschin
bfe6f6235f drivers/mmc/mv_sdhci.c: Fix build warning
Fix:
mv_sdhci.c: In function 'mv_sdh_init':
mv_sdhci.c:47:22: warning: the comparison will always
evaluate as 'true' for the address of 'mv_sdhci_writeb'
will never be NULL [-Waddress]

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Lei Wen <leiwen@marvell.com>
Cc: Andy Fleming <afleming@freescale.com>
Acked-by: Lei Wen <leiwen@marvell.com>
2012-01-08 21:28:16 -06:00
Macpaul Lin
31cb6db5db ftsdc010: improve performance and capability
This patch improve the performance by spliting flag examination code
in ftsdc010_send_cmd() into 3 functions.
This patch also reordered the function which made better capability to
some high performance cards against to the next version of ftsdc010
hardware.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2012-01-08 21:28:16 -06:00
Macpaul Lin
2c3fbf4cbe mmc: add host_caps checking avoid switch card improperly
Add a host capability checking to avoid the mmc stack
switch the card to HIGHSPEED mode when the card supports
HIGHSPEED while the host doesn't.

This patch avoid furthur transaction problem when the
mmc/sd card runs different mode to the host.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>
2012-01-08 21:28:16 -06:00
Jason Liu
4692708d45 i.mx: fsl_esdhc: add the i.mx6q support
The mmc host controller on the i.mx6q is called usdhc which
is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except
it adds one mix register to support debug/SD3.0 and move
the low bit 0-6 of XFERTYP register to the mix control reg
low bit 0-6. Thus on i.mx6q, we have the following compared
with the previous soc: (can refer to RM of chapter 56.3.3)

i.mx6q:
mix control:
bit 31 - bit 7: Added for debug/SD3.0 support
bit 6  - bit 0: move in the XFERTYP register bit 6-0 on previous soc
XFERTYP register:
bit 31 - bit 7: the same as before,
bit 6  - bit 0: no-use

previous soc
mix control: no
XFERTYP register:
bit 31 - bit 0: xfertype information

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2012-01-08 21:28:16 -06:00
Wolfgang Denk
d0b8feef8b Revert "common.h: remove value from bool defines"
This reverts commit 914c9ee971
which is causing tons of build warnings like
start.S:39:0: warning: "_LINUX_CONFIG_H" redefined [enabled by
default]
/home/wd/git/u-boot/work/include/common.h:28:0: note: this is the
location of the previous definition
/work/wd/tmp-ppc/nand_spl/board/freescale/mpc8315erdb/start.S:39:0:
warning: "_LINUX_CONFIG_H" redefined [enabled by default]
/home/wd/git/u-boot/work/include/common.h:28:0: note: this is the
location of the previous definition
etc.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-01-06 07:36:44 +01:00
Rob Herring
9a420986cc ARM: highbank: enable networking and pxe
This enables the XGMAC ethernet driver and networking related config
options.

Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2012-01-05 20:10:38 +01:00
Rob Herring
efdd731957 net: add Calxeda xgmac driver
This adds ethernet driver for Calxeda xgmac found on Highbank SOC.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

Fix: WARNING: __aligned(size) is preferred over
__attribute__((aligned(size)))
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-01-05 20:10:38 +01:00
David Wagner
dbee61db43 Correctly handle input files beginning with several newlines
Also, fix some comments (minor)

Signed-off-by: David Wagner <david.wagner@free-electrons.com>
2012-01-05 20:10:38 +01:00
Donggeun Kim
627182ea9d FAT: update the second FAT when writing a file
After susccessful write to the FAT partition,
fsck program may print warning message due to different FAT,
provided that the filesystem supports two FATs.

This patch makes the second FAT to be same with the first one
when writing a file.

Signed-off-by: Donggeun Kim <dg77.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2012-01-05 20:10:38 +01:00
Kyle Moffett
5dd95cf93d usb_storage: Fix EHCI "out of buffer pointers" with CD-ROM
When performing large bulk reads from a CD or DVD using the U-Boot
usb_storage driver, it generates requests of up to 20 blocks at a time.

With a standard 512-byte block size, that is 10240 bytes and within the
limit of U-Boot's EHCI driver (maximum 5 pages at 4k per page).

Unfortunately CD-ROM media has a 2048-byte blocksize, resulting in a
maximum transfer size of 40960 bytes, which does not fit.

Since the EHCI specification is impossibly obtuse and far beyond my
comprehension, I chose to dynamically compute the limit based on the
blocksize.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
2012-01-05 20:10:38 +01:00
Kyle Moffett
46236b1407 fs/fat: Improve error handling
The FAT filesystem fails silently in inexplicable ways when given a
filesystem with a block-size that does not match the device sector size.
In theory this is not an unsupportable combination but requires a major
rewrite of a lot of the filesystem.  Until that occurs, the filesystem
should detect that scenario and display a helpful error message.

This scenario in particular occurred on a 512-byte blocksize FAT fs
stored in an El-Torito boot volume on a CD-ROM (2048-byte sector size).

Additionally, in many circumstances the ->block_read method will not
return a negative number to indicate an error but instead return 0 to
indicate the number of blocks successfully read (IE: None).

The FAT filesystem should defensively check to ensure that it got all of
the sectors that it asked for when reading.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
2012-01-05 20:10:37 +01:00
Kyle Moffett
9813b750f3 fs/fat: Fix FAT detection to support non-DOS partition tables
The FAT filesystem code currently ends up requiring that the partition
table be a DOS MBR, as it checks for the DOS 0x55 0xAA signature on the
partition table (which may be Mac, EFI, ISO9660, etc) before actually
computing the partition offset.

This fixes support for accessing a FAT filesystem in an ISO9660 boot
volume (El-Torito format) by reordering the filesystem checks and
reading the 0x55 0xAA "DOS boot signature" and FAT/FAT32 magic number
from the first sector of the partition instead of from sector 0.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>

Fix build warning:  fat.c: In function 'fat_register_device':
fat.c:66:15: warning: variable 'found_partition' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-01-05 20:10:06 +01:00
Simon Glass
26784f1ecb ext2: Cache line align indirection buffers
Make ext2 use cache line aligned buffers for reading from the filesystem.
This is needed when caches are enabled because unaligned cache invalidates
are not safe.

Signed-off-by: Simon Glass <sjg@chromium.org>
2012-01-05 17:12:11 +01:00
Grant Erickson
aa701b9433 tools/env: allow overwrite of ethaddr on default
This patch allows the U-Boot user space companion utility, fw_setenv,
to overwrite the 'ethaddr' key/value pair if the current value is set
to a per-board-configured default.

This change allows 'fw_setenv' to match the behavior of 'setenv' /
'env set' on the U-Boot command line.

Signed-off-by: Grant Erickson <marathon96@gmail.com>
Fixed excessive white space.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2012-01-05 17:00:01 +01:00
Wolfgang Denk
145afab32c Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm:
  tegra2: Optimize out-of-tree build for Ventana.
  tegra: Move boards over to use arch-level board UART function
  tegra: Add support for UART init in cpu board.c
  tegra: Add a function mux feature
  tegra: add clock_ll_start_uart() to enable UART prior to reloc
  tegra: Move clock_early_init() to arch_cpu_init()
  tegra: Move cpu_init_cp15() to arch_cpu_init()
  arm: Tegra: Fix Harmony and Ventana builds in u-boot-tegra/master
  tegra: Fix build error in plutux, medcom
  tegra2: Add Avionic Design Medcom support.
  tegra2: Add Avionic Design Plutux support.
  tegra2: Add common Avionic Design Tamonten support.
  tegra2: Move tegra2_mmc_init() prototype to public header.
  tegra2: Change CONFIG_SYS_TEXT_BASE to 0x00108000.
  tegra2: Always build with USE_PRIVATE_LIBGCC=yes.
  tegra2: Plumb in SPI/UART switch code
  tegra2: spi: Support SPI / UART switch
  tegra2: Implement SPI / UART GPIO switch
  tegra2: Enable SPI environment on Seaboard
  tegra2: config: Enable SPI flash on Seaboard
  tegra2: spi: Add SPI driver for Tegra2 SOC
  tegra2: Add UARTB support
  tegra2: Tidy UART selection
  arm, davinci: Fix build warnings for cam_enc_4xx
  Devkit8000: Switch over to enable_gpmc_cs_config
  arm, davinci: Add support for generating AIS images to the Makefile
  mkimage: Fix variable length header support
  arm, da850evm: Add an SPL for SPI boot
  arm, davinci: Add SPL support for DA850 SoCs
  sf: Add spi_boot() to allow booting from SPI flash in an SPL
  spl: display_options.o is required for SPI flash support in SPL
  ARM: omap3: add support to Technexion twister board
  ARM: omap3: added common configuration for Technexion TAM3517
  vision2: Fix checkpatch warning
2012-01-05 16:38:50 +01:00
Horst Kronstorfer
72ebafbe2b tools/mkenvimage.c: Fix a merge issue
With bfcc40bb09 'optopt' was reverted.

Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com>
2012-01-05 16:36:44 +01:00
Igor Grinberg
6f403bad80 env: remove value from boolean defines
Several boolean defines have a value assigned.
Remove the value as defining the symbol is enough.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-01-05 16:35:54 +01:00
Igor Grinberg
914c9ee971 common.h: remove value from bool defines
Several boolean defines have a value assigned.
Remove the value as defining the symbol is enough.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Mike Frysinger <vapier@gentoo.org>
2012-01-05 16:35:29 +01:00
Igor Grinberg
bf95df44ff env: factor out the env_get_char_spec() function
env_get_char_spec() function is duplicated across multiple environment
files.
Remove the duplication by providing a default implementation.
Add "weak" declaration, so the default implementation can be overridden.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
2012-01-05 16:34:10 +01:00
Stefano Babic
33e1e01820 fpga: Spartan-3: let print the progress if configured
CONFIG_SYS_FPGA_PROG_FEEDBACK was already introduced to print
the current status of FPGA loading - an undef in the code made this
CONFIG_ useless.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-01-05 16:20:12 +01:00
Stefano Babic
06297db066 FPGA: use debug() instead of module debug printf
Replace also __FUNCTION__ with standard __func__

Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-01-05 16:19:20 +01:00
Stefano Babic
28cdc1c8e2 fpga: add definition for Xilinx Spartan-6 XC6SLX4
Signed-off-by: Stefano Babic <sbabic@denx.de>
2012-01-05 16:18:30 +01:00