The phy_connect_dev(...) function from phy.c does all the handling
(inclusive catching fixed-link).
So we drop here the single steps and call just phy_connect_dev(...).
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Currently the spl system calls nand_init which does nothing.
It isn't until an attempt to load from NAND that it gets initialized.
Subsequent attempts to load just skip the initialization because
NAND is already initialized.
This moves the contents of mxs_nand_init to nand_init. In the event
of an error, it clears the number of nand chips found. Any
attempts to use nand will check if there are nand chips available
instead of actually doing the initialization at that time. If there
are none, it will return an error to the higher level calls.
Signed-off-by: Adam Ford <aford173@gmail.com>
Kconfig allows boards to configured with DM_SERIAL and still
have SPL_DM_SERIAL disabled. This patch changes the ifdef's
to CONFIG_IS_ENABLED to allow the modes to differ between
SPL and U-Boot.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix an error with the serial communication on boards with a very small
UART buffer which leads to a stalled system.
Provide an X86 reset driver for the UEFI runtime.
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Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-boot
Pull request for UEFI system for v2019.04-rc4
Fix an error with the serial communication on boards with a very small
UART buffer which leads to a stalled system.
Provide an X86 reset driver for the UEFI runtime.
According to datasheet, the output on LDO regulators will start
appearing after 10-15 us.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Changing voltage and enabling regulator might require delays so the
regulator stabilizes at expected level.
Add support for "regulator-ramp-delay" binding which can introduce
required time to both enabling the regulator and to changing the
voltage.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
When stopping the ADC_V2_CON1_STC_EN should be cleared.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Our selftest will soon test the actual runtime reset function rather than
the boot time one. For this, we need to ensure that the runtime version
actually succeeds on x86 to keep our travis tests work.
So this patch implements an x86 runtime reset function. It is missing
shutdown functionality today, but OSs usually implement that via ACPI
and this function does more than the stub from before, so it's at least
an improvement.
Eventually we will want to have full DM functionality in runtime services.
But this fixes a travis failure and doesn't clutter the code too heavily, so
we should pull it in without the amazing new RTS DM framework.
Signed-off-by: Alexander Graf <agraf@suse.de>
Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.
This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The debug print is missing a newline, add it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.
Which would eventually used in sunxi_emac.c driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This pull request contains bugfixes for rcar_i2c, rcar_ii2c and
i2c_cdns driver.
Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek
is a bugfix for arm64 builds, as discussed with Marek on list.
Fix typo in axp_set_dldo() so that it correctly uses AXP818_DLDO1_CTRL
register to configure the voltage instead of setting AXP818_ELDO1_CTRL
register which is obviously incorrect.
Signed-off-by: Ondřej Jirman <megous@megous.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Cosmetic change. Any call to the recover function would need to do the
same check afterwards, so it's sensible to make it part of the function.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
It needs to be done for both reads and writes, so do it at rcar_i2c_xfer
to avoid duplication.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Fix rcar_i2c_xfer return value, previously it was always returning
-EREMOTEIO when dealing with errors from calls to the read/write
functions.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Do the reset before clearing the MSR, otherwise it may result in a read
or write operation instead if the start condition is repeated.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Document the meaning of macros related to registers and values to be
written to them.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Setting up the delay only needs to be done once; move it to
rcar_i2c_set_speed so it's done at initialization time.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This patch adds support for handling arbitration lost
in case of multi master mode. When an arbitration lost
is detected, it retries for 10 times before failing.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The arbitration lost interrupt was not getting cleared
while clearing interrupts. This patch fixes this by adding
arbitration lost interrupt as well during clear. This patch
also removes hardcoded value and defined a macro for it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Add support for R-Car Gen3 SoCs into the driver, which encompases
the Gen3 SoC extra timing register handling and 64bit build fixes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Read ICSR only once to avoid missing interrupts. This happens on R8A7791
Porter during reset, when reading the PMIC register 0x13, which may fail
sometimes because of the missed DTE interrupt.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Now the same SPI controller driver is reusable in all Allwinner
SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c
which eventually look like a common sunxi driver.
Also update the function, variable, structure names in driver from
sun4i into sunxi.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
- drop unused macros.
- use base instead of base_addr, for better code readability
- move .probe and .ofdata_to_platdata functions in required
places to add platdata support in future.
- use sentinel sun4i_spi_ids.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The usual SPI transmission protocol in Allwinner A10 and A31
controllers share similar context with minimal changes in register
offsets along with few additional register bits on A31.
So, add A31 spi controller support in existing sun4i_spi with A31
specific register offsets and bits.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
Clock disablement could be done while releasing the bus transfer, but
the existing code doesn't disable the clocks it only taken care of clock
enablement globally in probe.
So to make a proper clock handling, the clocks should enable it in claim
and disable it in release.
This patch would also do that change, by enable and disable clock in
proper order.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Support fifo_depth via drvdata instead of macro definition, this would
eventually reduce another macro definition for new SPI controller fifo
depth support addition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave remains nearly similar.
Add enum offsets for register set and register bits, so-that
it can access both classes of SPI controllers.
Assign same control register for global, transfer and fifo control
registers to make the same code compatible with A31 SPI controller.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
Allwinner SoCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
To drain rx fifo the fifo need to poll for how much data has
been filled up in rx fifo.
To achieve this, the current code is using wait_for_bit logic
on control register with exchange burst mode mask, which is not
a proper way of waiting for fifo filled up.
So, add code for polling rxfifo to be filled up using fifo
status register.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
With current order of include files, the file designware_spi.c
can't see that the struct global_data has the member
board_type when CONFIG_BOARD_TYPES is defined. By not seeing this
then all the members are shifted in the struct global_data.
So when the driver is trying to read from device tree blob, it
would pass the wrong address to the function 'fdtdev_get_int'.
This will make to use the default frequency 500000.
The fix consists of changing the order of include files in
designware_spi.c to include first common.h file.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Since the datasheet Rev.1.00 has an error about the USB ID pin name,
this patch revises it.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50,
the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected,
and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0
bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are
selected.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
According to the R-Car Gen3 Hardware Manual Rev 1.50, the MOD_SEL0
bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are
selected.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR /
MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was
confirmed in the R-Car Gen3 Hardware Manual Rev.1.50.
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
