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20 commits

Author SHA1 Message Date
Eric Nelson
a425bf7281 ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines
The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.

Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.

Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.

Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29 16:40:37 +01:00
Eric Nelson
48c7d4379b mx6: ddr: add routine to return DDR calibration data
Add routine mmdc_read_calibration() to return the output of DDR
calibration. This can be used for debugging or to aid in construction
of static memory configuration.

This routine will be used in a subsequent patch set adding a virtual
"mx6memcal" board, but could also be useful when gathering statistics
during an initial production run.

Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29 16:40:25 +01:00
Eric Nelson
7f17fb7400 mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
The DDR calibration routines have scattered support for bus
widths other than 64-bits:

-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.

Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.

This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2016-11-29 16:40:12 +01:00
Eric Nelson
c8c3515508 imx: mx6: ddr: add register MPZQLP2CTL for LPDDR2
Add constants for the MPZQLP2CTL DDR register for both
banks to allow setting the LPDDR2 timing values in
.cfg files using a named constant instead of hex addresses
as is currently done in mx6slevk and other board files.

Signed-off-by: Eric Nelson <eric@nelint.com>
2016-11-29 16:38:10 +01:00
Fabio Estevam
edf0093732 mx6: ddr: Allow changing REFSEL and REFR fields
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.

Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:

$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4      0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800

So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.

Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06 18:22:48 +02:00
Marek Vasut
d339f16911 arm: imx6: Add DDR3 calibration code for MX6 Q/D/DL
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2016-02-02 20:58:46 +01:00
Peng Fan
eb796cbb69 imx: mx6: ddr: add LPDDR2 support
Add LPDDR2 support:
1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2.
2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to
   mx6_ddr3_cfg, but still keep it a single one for easy to choose
   parameters for LPDDR2.
3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC.
4. Update comments.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-02 15:34:12 +02:00
Peng Fan
f2ff834365 imx: mx6: ddr init MMDC according to ddr_type
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.

Initialize ddr_type for different boards which enable SPL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
003fa83c43 imx: mx6: ddr add an entry ddr_type for mx6_ddr_sysinfo
Add ddr_type entry for mx6_ddr_sysinfo. It will be used for
differenrate DDR3 and LPDDR2.

Introduce an enum type for ddr_type.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-02 15:34:12 +02:00
Peng Fan
775d591f5d imx: mx6: ddr add mpzqlp2ctl entry
Add mpzqlp2ctl entry for mx6_mmdc_calibration.
MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2015-09-02 15:34:12 +02:00
Peng Fan
1b811e285c imx: mx6: ddr add dram io configuration and header file for i.MX6SL
Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs.
Add a new function mx6sl_dram_iocfg to configure dram io.
Add header file to define macros for register address.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
43d9dc4136 imx: mx6: ddr add more register entry for mmdc_p_regs
Add more register entry for MMDC structure.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2015-09-02 15:34:12 +02:00
Peng Fan
a462c34602 imx:mx6ul add dram spl configuration and header file
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
   only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
   runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
   IO configuration.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-08-02 11:05:09 +02:00
Tim Harvey
78c5a18087 arm: mx6: ddr: add pd_fast_exit flag to system information
DDR3 has a special Precharge power-down mode: fast-exit vs slow-exit.

In slow-exit mode the DLL is off but in some quiescent state that makes it easy
to turn on again in tXPDLL cycles (about 10tCK) vs the full tDLLK (512tCK).
In fast-exist mode the DLL is maintained such that it is ready again in about
3tCK.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2015-04-22 14:35:35 +02:00
Peng Fan
d9efd47c03 imx:mx6sx add dram io configure for mx6sx
Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs.
Add a new function mx6sx_dram_iocfg to configure dram io.

Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1
to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1
effects as "mmdc1->entry=value".

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-01-22 09:55:47 +01:00
Fabio Estevam
05d54b827f mx6: Add support for the mx6solox variant
mx6solox is the newest member of the mx6 family.

Some of the new features on this variants are:
- Cortex M4 microcontroller (besides the CortexA9)
- Dual Gigabit Ethernet

Add the initial support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-07-10 15:29:16 +02:00
Tim Harvey
fe0f7f7842 mx6: add mmdc configuration for MX6Q/MX6DL
- add function for configuring iomux based on board-specific regs
- add function for configuring mmdc based on board-specific and
  chip-specific data

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-06-06 10:07:26 +02:00
Tim Harvey
8d05b161fc mx6: add structs for mmdc and ddr iomux registers
Add memory-mapped structures for MMDC iomux and configuration. Note that whi
the MMDC configuration registers are common between the IMX6DQ
(IMX6DUAL/IMX6QUAD) and IMX6SDL (IMX6SOLO/IMX6DUALLITE) types the iomux
registers differ. This requires two sets of structures.

Add structures to describe DDR3 device information, system information
(memory layout, etc), and MMDC calibration registers that can be used to
configure the MMDC dynamically.

We define these structures for SPL builds instead of including mx6q-ddr.h an
mx6dl-ddr.h which use the same namespace and are only useful for imximage cf
files.

Cc: Stefan Roese <sr@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Andy Ng <andreas2025@gmail.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Tapani Utriainen <tapani@technexion.com>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-06-06 10:07:25 +02:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Eric Nelson
690417236f i.MX6: Add DDR controller registers
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-03-07 16:43:47 +01:00