Commit graph

49053 commits

Author SHA1 Message Date
Masahiro Yamada
c21f58548c ARM: uniphier: deassert RST_n of eMMC device for LD11/LD20
For LD11 and LD20 SoCs, the RST_n pin is asserted by default.  If
the EXT_CSD[162], bit[1:0] (RST_n_ENABLE) is fused, the eMMC device
would stay in the reset state until its RST_n pin is deasserted by
software.

Currently, this is cared by an ad-hoc way because the eMMC hardware
reset provider is not supported in U-Boot for now.  This code should
be re-written once the "mmc-pwrseq-emmc" binding is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Kotaro Hayashi
04f3da3936 ARM: uniphier: add DRAM PHY clock duty adjustment for LD20 SoC
If the DRAM clock duty does not meet the allowable tolerance,
it is marked in an efuse register.  If the register is fused,
the boot code should compensate for the DRAM clock duty error.

Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com>
[masahiro: simplify code, add git-log]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
dd38374d2f ARM: uniphier: remove dram_nr_ch from board parameters
This parameter is redundant because we can know the number of
channels by checking if dram_ch[2].size is zero.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
784548efb2 ARM: uniphier: rework spl_boot_device() and related code
The current implementation has ugly switch statements here and there,
and duplicates similar code.  Rework it using table lookups for SoC
data and reduce code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
81c847bf38 ARM: uniphier: move spl_boot_mode() to a separate file
The spl_boot_mode() is unrelated to the other code in this file.
Besides, this function is only called from common/spl/spl_mmc.c,
so it is reasonable to guard with CONFIG_SPL_MMC_SUPPORT.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
e5957e8d69 ARM: uniphier: move MMC code to a separate file
Currently, arch/arm/mach-uniphier/boot-mode/boot-mode.c is messed up
with unrelated code; there is no reason why the "mmcsetn" command
must be placed in this file.

Split out the MMC code into arch/arm/mach-uniphier/mmc-first-dev.c.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
5c8c6da132 ARM: uniphier: disable CONFIG_MTD_NOR_FLASH
This feature is seldom used these days on UniPhier boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
c276953885 ARM: dts: uniphier: drop u-boot, dm-pre-reloc from system-bus pinctrl node
Since commit 26b09c022a ("ARM: uniphier: move SBC and Support Card
init code to U-Boot proper"), SPL does not need pin-mux settings for
the System Bus.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
7728f0c68d ARM: uniphier: rename second stage loader name
For the memory footprint reason, the Boot ROM can not load the ARM
Trusted Firmware BL1 directly when Trusted Board Boot is enabled.
The second stage loader is Socionext's own firmware, so rename it
for clarification.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
6a6b9d5dfd pinctrl: uniphier: support pin configuration
Support the following DT properties:
  "bias-disable"
  "bias-pull-up"
  "bias-pull-down"
  "bias-pull-pin-default"
  "input-enable"
  "input-disable"

My main motivation is to support pull up/down biasing.  For Pro5 and
later SoCs, the pupdctrl register number is the same as the pinmux
number, so this feature can be supported without having big pin
tables.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
1b280978c0 ARM: uniphier: enable generic EHCI driver for uniphier_v8_defconfig
The LD11 SoC is equipped with USB EHCI controllers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
04cd4e7215 ARM: uniphier: remove DRAM base address from board parameters
The base address of each DRAM channel can be calculated from other
parameters, so does not need hard-coding.  What we need is the size
of each DRAM channel and DRAM_SPARSE flag to decide the start address
of DRAM channel 1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
cf3175bcd8 ARM: uniphier: update README.uniphier for latest build instruction
Since commit c0efc3140e ("ARM: uniphier: change CONFIG_SPL_PAD_TO
to 128KB"), the u-boot.bin should be burned at the offset 0x20000.
I missed to update README.uniphier in that commit.  Now updating.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
6fc849148a ARM: uniphier: print Support Card info very late
Since commit 26b09c022a ("ARM: uniphier: move SBC and Support Card
init code to U-Boot proper"), the System Bus is initialized by
board_init().  The show_board_info() is called from board_init_f()
by default, so the revision register of the Micro Support Card may
not be accessed at this point.  Show its revision after the System
Bus is initialized.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
87c3308cbf ARM: uniphier: skip memreserve of unused DRAM bank of LD20
Now the "for" loop here iterates on the detected memory banks.
It must skip unused DRAM banks.

Fixes: c995f3a3c5 ("ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoC")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
0f5bf09cf1 ARM: uniphier: correct spelling of "invalid"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
bed1624d0d ARM: uniphier: skip MEMCONF ch2 parsing if CH2_DISABLE bit is set
If SG_MEMCONF_CH2_DISABLE bit is set, the DRAM channel 2 is unused.
The register settings for the ch2 should be ignored.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Masahiro Yamada
14bb7a4e37 ARM: uniphier: revive accidentally removed dcache_disable()
Commit a8e6300d48 ("ARM: uniphier: refactor spl_init_board()")
accidentally dropped dcache_disable() call.  Since then, the SPL of
LD11 and LD20 failed to load U-Boot proper.

Fixes: a8e6300d48 ("ARM: uniphier: refactor spl_init_board()")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 08:37:56 +09:00
Fabio Estevam
b24cf8540a video: mxsfb: Fix reset hang when videomode variable is not present
Currently the system hangs when the 'videomode' variable is not present
and a reset command is issued:

=> setenv videomode
=> saveenv
=> reset

(Board hangs)

lcdif_power_down() assumes that the LCDIF controller has been properly
configured and enabled, which may not be true.

To fix this issue check whether panel.frameAdrs has been initialized and
in case it has not been initialized, do not continue with the LCDIF
powerdown sequence.

Tested on a imx7dsabresd board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2017-02-22 21:47:59 +01:00
Tom Rini
4d6f9e0d21 Merge git://git.denx.de/u-boot-x86 2017-02-22 10:27:37 -05:00
Andy Shevchenko
308c75e08d x86: Intel MID platforms has no microcode update
There is no microcode update available for SoCs used on Intel MID
platforms.

Use conditional to bypass it.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-02-21 15:10:56 +08:00
Vincent Tinelli
20bfac0599 x86: zImage: add Intel MID platforms support
Intel MID platform boards have special treatment, such as boot parameter
setting.

Assign hardware_subarch accordingly if CONFIG_INTEL_MID is set.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-02-21 15:10:50 +08:00
Andy Shevchenko
7a96fd8ef0 x86: Introduce INTEL_MID quirk option
Intel Mobile Internet Device (MID) platforms have special treatment in
some cases, such as CPU enumeration or boot parameters configuration.

Besides that several drivers are specifically developed for the IP
blocks found on Intel MID platforms. Those drivers will be dependent to
this option.

Here we introduce specific quirk option for such cases.

It is supposed to be selected by Intel MID platform boards, for example,
Intel Edison.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-02-21 15:10:46 +08:00
J. Tang
3c03f4928e x86: Force 32-bit jumps in interrupt handlers
Depending upon the compiler used, IRQ entries could vary in sizes. With
GCC 5.x, the code generator will use short jumps for some IRQ entries
but near jumps for others. For example, GCC 5.4.0 generates the
following:

$ objdump -d interrupt.o
<snip>
00000207 <irq_18>:
207:   6a 12                   push   $0x12
209:   eb 85                   jmp    190 <irq_common_entry>

0000020b <irq_19>:
20b:   6a 13                   push   $0x13
20d:   eb 81                   jmp    190 <irq_common_entry>

0000020f <irq_20>:
20f:   6a 14                   push   $0x14
211:   e9 7a ff ff ff          jmp    190 <irq_common_entry>

00000216 <irq_21>:
216:   6a 15                   push   $0x15
218:   e9 73 ff ff ff          jmp    190 <irq_common_entry>

This causes a problem in cpu_init_interrupts(), because the IDT setup
assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit
jumps, so this previously was not a problem.

The fix is to force 32-bit near jumps for all entries within the
inline assembly. This works for GCC 5.x, and 4.x was already using
that form of jumping.

Signed-off-by: Jason Tang <tang@jtang.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-21 14:53:29 +08:00
Markus Niebel
dc05e47a10 tqma6: [cosmetic] sanitize environment defines
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2017-02-19 17:16:51 +01:00
Markus Niebel
e7203d77f6 tqma6: fix rounding in env
need to add before div in mmc update scripts. Otherwise we could
write one block more ba acident

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2017-02-19 17:16:51 +01:00
Markus Niebel
34713901ad mx6: tqma6: add rootfsmode environment for mmc / sd
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2017-02-19 17:16:51 +01:00
Markus Niebel
0b14f1a615 mx6: tqma6: fix typo in env
there was a double bracketed var ref. fix this.

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2017-02-19 17:16:51 +01:00
Markus Niebel
dd9908da3f imx6: tqma6: rely on default setting for tftp and nfs
Playing with USB-to-Ethernet dongles it turns out,
that these will not work with special settings

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2017-02-19 17:16:51 +01:00
Markus Niebel
9e9846a484 arm: imx6: tqma6: add configurable CMA size
depending on the use case different CMA sizes are
needed for linux. Add env var to enable passing CMA size
via kernel command line

Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
2017-02-19 17:16:51 +01:00
Andrey Yurovsky
f78038dc0d mtd: nand: build MXS driver for MX7 as well
The i.MX7 has the same GPMI controller as i.MX6 and is covered by the MXS
driver. Tell Kconfig that we can use this driver on the MX7 platform (the MXS
driver already has the few i.MX7-specific changes needed for basic operation
and the board itself sets the pinmux correctly).

Tested on i.MX7D with the Sabre board and a NAND Flash soldered to U12.

Signed-off-by: Andrey Yurovsky <yurovsky@gmail.com>
2017-02-19 16:20:28 +01:00
Peter Robinson
774eb2dbc0 mx6sx: udoo_neo: Enable distro boot options in config
The include/configs/udoo_neo.h already includes the distro defaults
include files so it seems the board was missed in the move to the
config file, whether that in initial commit or conversion, so
enable the option now and remove duplicated settings.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2017-02-19 16:19:54 +01:00
Peter Robinson
276ad0650c mx6sx: udoo_neo: use different load address for ramdisk
The fdt_addr and ramdisk_addr_r are currently both defined to
0x83000000 and that's not going to work well for anyone. Move
the ramdisk_addr_r to 0x84000000.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
2017-02-19 16:19:41 +01:00
Peter Robinson
f902802f65 mx6sx: udoo_neo: Define the default serial console
Standard boot processes including distro boot generally expect the
default console to be defined.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
2017-02-19 16:19:26 +01:00
Tom Rini
79be18a60f Drop CONFIG_ENABLE_VBOOT
This is no longer used anywhere.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-02-17 19:47:53 -05:00
Andrew F. Davis
66c246cce7 ARM: DRA7xx: Fix memory allocation overflow
When using early malloc the allocated memory can overflow into the SRAM
scratch space, move NON_SECURE_SRAM_IMG_END down a bit to allow more
dynamic allocation at the expense of a slightly smaller maximum image
size.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-02-17 17:24:35 -05:00
ahaslam@baylibre.com
4aac44be11 da850: Add instructions to copy AIS image to an MMC card
The da850 soc's can boot from a external mmc card, but
the AIS image should be written to the correct sector.

Add instructions to copy the AIS image to a MMC card.

Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-02-17 17:24:35 -05:00
Semen Protsenko
7a2af751a0 arm: am57xx: Set serial# variable
serial# variable is used to correctly display device ID in
"fastboot devices". It also can be used further for displaying device ID
in "adb devices" (should be passed as "androidboot.serialno" to kernel
cmdline, via "bootargs" variable).

Serial number generating algorithm is described at [1].

[1] http://lists.denx.de/pipermail/u-boot/2015-March/207462.html

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-02-17 17:24:34 -05:00
Dalon Westergreen
949123e30a SPL: Move SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to Kconfig
Added SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION and
SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION to Kconfig.

Due to SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION being moved to
Kconfig the board defconfigs for db-88f6820-gp_defconfig
kc1_defconfig and sniper_defconfig need to be updated.

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-02-17 14:15:15 -05:00
Dalon Westergreen
f0fb4fa7d5 SPL: add support to boot from a partition type
the socfpga bootrom supports mmc booting from either a raw image
starting at 0x0, or from a partition of type 0xa2.  This patch
adds support for locating the boot image in the first type 0xa2
partition found.

Assigned a partition number of -1 will cause a search for a
partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
and use it to find the u-boot image

Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-02-17 14:15:14 -05:00
Andrew F. Davis
bc1e0dd947 arm: omap5: Fix generation of reserved-memory DT node
When the node 'reserved-memory' is not defined in the DT we fail
to add needed properties. We also fail to move 'offs' to point to
the new node. Fix these here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-02-17 14:15:12 -05:00
Tom Rini
645cb46e2b fsl_i2c.c: Fix warning on gcc-6.x
With gcc-6.x we see:
drivers/i2c/fsl_i2c.c:86:3: warning: ‘fsl_i2c_speed_map’ defined but not
used [-Wunused-const-variable=]

The easy way to fix this is that since we only use fsl_i2c_speed_map at
all on __M68K__ move the existing guards around slightly.

Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
2017-02-17 14:15:12 -05:00
Stefan Herbrechtsmeier
61e745d131 mmc: zynq: Add fdt max-frequency support
The maximum supported peripheral clock frequency of the zynq depends on
the IO routing. The MIO and EMIO support a maximum frequency of 50 MHz
respectively 25 MHz. Use the max-frequency value of the device tree to
determine the maximal supported peripheral clock frequency.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:47 +01:00
Stefan Herbrechtsmeier
e0f4de1afc mmc: zynq: Determine base clock frequency via clock framework
The zynq_sdhci controller driver use CONFIG_ZYNQ_SDHCI_MAX_FREQ as base
clock frequency but this clock is not fixed and depends on the hardware
configuration. Additionally the value of CONFIG_ZYNQ_SDHCI_MAX_FREQ
doesn't match the real base clock frequency of SDIO_FREQ. Use the clock
framework to determine the frequency at run time.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:47 +01:00
Stefan Herbrechtsmeier
9bb803d5b0 clk: zynq: Add optional ethernet emio clock source support
Add support for the optional ethernet emio clock source to the zynq
clock framework driver.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
781745bd87 zynq: Move zynq to clock framework
Move the zynq to clock framework and remove unused functions as well as
the CONFIG_ZYNQ_PS_CLK_FREQ configuration.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
3a64b25364 clk: zynq: Add zynq clock framework driver
Add a clock framework driver for the zynq platform. The driver is based
on the platform zynq clock driver but reworked to use static functions
instead of run-time generated objects even for unused clocks.
Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the
ps-clk-frequency from the device tree.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
f96fccba71 zynq: Remove zynq_clk_get_name function
The zynq_clk_get_name function is only used once inside the clock
driver. Replace the function call with the one-line code.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
e18c0f667e zynq: Move static clock names into separate array
The clock names are static and correspond to the clock id. Separate
them from the dynamic filled clock array.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00
Stefan Herbrechtsmeier
c7abb824dd zynq: Add clk framework support to zynq timer
If available use the clock framework to calculate the clock rate of the
zynq timer.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-02-17 10:22:46 +01:00