mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-18 06:58:54 +00:00
ARM: uniphier: move SBC and Support Card init code to U-Boot proper
Initialize SBC and Support Card in U-Boot proper instead of SPL. We may run different firmware (ex. ARM Trusted Firmware) before U-Boot, and basic SoC initialization may be done there. In that case, SPL may not be used. The motivation for preparing SBC and Support Card in SPL was to use LED for early debugging, but this is not mandatory to boot SoCs. With this commit, LED will be unavailable in SPL, but we can use a debug serial instead. So, this change will not be a big deal. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
parent
a8e6300d48
commit
26b09c022a
3 changed files with 19 additions and 27 deletions
|
@ -7,7 +7,6 @@ ifdef CONFIG_SPL_BUILD
|
|||
obj-y += spl_board_init.o
|
||||
obj-y += memconf.o
|
||||
obj-y += bcu/
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
|
||||
|
||||
else
|
||||
|
||||
|
@ -17,6 +16,9 @@ obj-y += board_init.o
|
|||
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
|
||||
obj-y += reset.o
|
||||
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ micro-support-card.o
|
||||
obj-y += pinctrl-glue.o
|
||||
|
||||
endif
|
||||
|
||||
obj-y += boards.o
|
||||
|
@ -24,9 +26,7 @@ obj-y += soc_info.o
|
|||
obj-y += boot-mode/
|
||||
obj-y += clk/
|
||||
obj-y += dram/
|
||||
obj-y += pinctrl-glue.o
|
||||
|
||||
obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
|
||||
obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
|
||||
|
||||
obj-$(CONFIG_CPU_V7) += arm32/
|
||||
|
|
|
@ -81,6 +81,7 @@ static void uniphier_ld20_misc_init(void)
|
|||
struct uniphier_initdata {
|
||||
enum uniphier_soc_id soc_id;
|
||||
bool nand_2cs;
|
||||
void (*sbc_init)(void);
|
||||
void (*pll_init)(void);
|
||||
void (*clk_init)(void);
|
||||
void (*misc_init)(void);
|
||||
|
@ -91,6 +92,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_SLD3,
|
||||
.nand_2cs = true,
|
||||
.sbc_init = uniphier_sbc_init_admulti,
|
||||
.pll_init = uniphier_sld3_pll_init,
|
||||
.clk_init = uniphier_ld4_clk_init,
|
||||
},
|
||||
|
@ -99,6 +101,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_LD4,
|
||||
.nand_2cs = true,
|
||||
.sbc_init = uniphier_ld4_sbc_init,
|
||||
.pll_init = uniphier_ld4_pll_init,
|
||||
.clk_init = uniphier_ld4_clk_init,
|
||||
},
|
||||
|
@ -107,6 +110,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_PRO4,
|
||||
.nand_2cs = false,
|
||||
.sbc_init = uniphier_sbc_init_savepin,
|
||||
.pll_init = uniphier_pro4_pll_init,
|
||||
.clk_init = uniphier_pro4_clk_init,
|
||||
},
|
||||
|
@ -115,6 +119,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_SLD8,
|
||||
.nand_2cs = true,
|
||||
.sbc_init = uniphier_ld4_sbc_init,
|
||||
.pll_init = uniphier_ld4_pll_init,
|
||||
.clk_init = uniphier_ld4_clk_init,
|
||||
},
|
||||
|
@ -123,6 +128,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_PRO5,
|
||||
.nand_2cs = true,
|
||||
.sbc_init = uniphier_sbc_init_savepin,
|
||||
.clk_init = uniphier_pro5_clk_init,
|
||||
},
|
||||
#endif
|
||||
|
@ -130,6 +136,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_PXS2,
|
||||
.nand_2cs = true,
|
||||
.sbc_init = uniphier_pxs2_sbc_init,
|
||||
.clk_init = uniphier_pxs2_clk_init,
|
||||
},
|
||||
#endif
|
||||
|
@ -137,6 +144,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_LD6B,
|
||||
.nand_2cs = true,
|
||||
.sbc_init = uniphier_pxs2_sbc_init,
|
||||
.clk_init = uniphier_pxs2_clk_init,
|
||||
},
|
||||
#endif
|
||||
|
@ -144,6 +152,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_LD11,
|
||||
.nand_2cs = false,
|
||||
.sbc_init = uniphier_ld11_sbc_init,
|
||||
.pll_init = uniphier_ld11_pll_init,
|
||||
.clk_init = uniphier_ld11_clk_init,
|
||||
.misc_init = uniphier_ld11_misc_init,
|
||||
|
@ -153,6 +162,7 @@ struct uniphier_initdata uniphier_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_LD20,
|
||||
.nand_2cs = false,
|
||||
.sbc_init = uniphier_ld11_sbc_init,
|
||||
.pll_init = uniphier_ld20_pll_init,
|
||||
.misc_init = uniphier_ld20_misc_init,
|
||||
},
|
||||
|
@ -187,6 +197,12 @@ int board_init(void)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
initdata->sbc_init();
|
||||
|
||||
support_card_init();
|
||||
|
||||
led_puts("U0");
|
||||
|
||||
if (IS_ENABLED(CONFIG_NAND_DENALI)) {
|
||||
ret = uniphier_pin_init(initdata->nand_2cs ?
|
||||
"nand2cs_grp" : "nand_grp");
|
||||
|
|
|
@ -17,7 +17,6 @@ struct uniphier_spl_initdata {
|
|||
enum uniphier_soc_id soc_id;
|
||||
void (*bcu_init)(const struct uniphier_board_data *bd);
|
||||
void (*early_clk_init)(void);
|
||||
void (*sbc_init)(void);
|
||||
int (*dpll_init)(const struct uniphier_board_data *bd);
|
||||
int (*memconf_init)(const struct uniphier_board_data *bd);
|
||||
void (*dram_clk_init)(void);
|
||||
|
@ -30,7 +29,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
.soc_id = SOC_UNIPHIER_SLD3,
|
||||
.bcu_init = uniphier_sld3_bcu_init,
|
||||
.early_clk_init = uniphier_sld3_early_clk_init,
|
||||
.sbc_init = uniphier_sbc_init_admulti,
|
||||
.dpll_init = uniphier_sld3_dpll_init,
|
||||
.memconf_init = uniphier_memconf_3ch_no_disbit_init,
|
||||
.dram_clk_init = uniphier_sld3_dram_clk_init,
|
||||
|
@ -42,7 +40,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
.soc_id = SOC_UNIPHIER_LD4,
|
||||
.bcu_init = uniphier_ld4_bcu_init,
|
||||
.early_clk_init = uniphier_sld3_early_clk_init,
|
||||
.sbc_init = uniphier_ld4_sbc_init,
|
||||
.dpll_init = uniphier_ld4_dpll_init,
|
||||
.memconf_init = uniphier_memconf_2ch_init,
|
||||
.dram_clk_init = uniphier_sld3_dram_clk_init,
|
||||
|
@ -53,7 +50,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_PRO4,
|
||||
.early_clk_init = uniphier_sld3_early_clk_init,
|
||||
.sbc_init = uniphier_sbc_init_savepin,
|
||||
.dpll_init = uniphier_pro4_dpll_init,
|
||||
.memconf_init = uniphier_memconf_2ch_init,
|
||||
.dram_clk_init = uniphier_sld3_dram_clk_init,
|
||||
|
@ -65,7 +61,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
.soc_id = SOC_UNIPHIER_SLD8,
|
||||
.bcu_init = uniphier_ld4_bcu_init,
|
||||
.early_clk_init = uniphier_sld3_early_clk_init,
|
||||
.sbc_init = uniphier_ld4_sbc_init,
|
||||
.dpll_init = uniphier_sld8_dpll_init,
|
||||
.memconf_init = uniphier_memconf_2ch_init,
|
||||
.dram_clk_init = uniphier_sld3_dram_clk_init,
|
||||
|
@ -76,7 +71,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_PRO5,
|
||||
.early_clk_init = uniphier_sld3_early_clk_init,
|
||||
.sbc_init = uniphier_sbc_init_savepin,
|
||||
.dpll_init = uniphier_pro5_dpll_init,
|
||||
.memconf_init = uniphier_memconf_2ch_init,
|
||||
.dram_clk_init = uniphier_pro5_dram_clk_init,
|
||||
|
@ -87,7 +81,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_PXS2,
|
||||
.early_clk_init = uniphier_sld3_early_clk_init,
|
||||
.sbc_init = uniphier_pxs2_sbc_init,
|
||||
.dpll_init = uniphier_pxs2_dpll_init,
|
||||
.memconf_init = uniphier_memconf_3ch_init,
|
||||
.dram_clk_init = uniphier_pxs2_dram_clk_init,
|
||||
|
@ -98,7 +91,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_LD6B,
|
||||
.early_clk_init = uniphier_sld3_early_clk_init,
|
||||
.sbc_init = uniphier_pxs2_sbc_init,
|
||||
.dpll_init = uniphier_pxs2_dpll_init,
|
||||
.memconf_init = uniphier_memconf_3ch_init,
|
||||
.dram_clk_init = uniphier_pxs2_dram_clk_init,
|
||||
|
@ -109,7 +101,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_LD11,
|
||||
.early_clk_init = uniphier_ld11_early_clk_init,
|
||||
.sbc_init = uniphier_ld11_sbc_init,
|
||||
.dpll_init = uniphier_ld11_dpll_init,
|
||||
.memconf_init = uniphier_memconf_2ch_init,
|
||||
.dram_clk_init = uniphier_ld11_dram_clk_init,
|
||||
|
@ -120,7 +111,6 @@ static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
|
|||
{
|
||||
.soc_id = SOC_UNIPHIER_LD20,
|
||||
.early_clk_init = uniphier_ld11_early_clk_init,
|
||||
.sbc_init = uniphier_ld11_sbc_init,
|
||||
.dpll_init = uniphier_ld20_dpll_init,
|
||||
.memconf_init = uniphier_memconf_3ch_init,
|
||||
.dram_clk_init = uniphier_ld20_dram_clk_init,
|
||||
|
@ -165,45 +155,31 @@ void spl_board_init(void)
|
|||
if (initdata->bcu_init)
|
||||
initdata->bcu_init(bd);
|
||||
|
||||
initdata->sbc_init();
|
||||
|
||||
initdata->early_clk_init();
|
||||
|
||||
support_card_init();
|
||||
|
||||
led_puts("L0");
|
||||
|
||||
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
||||
preloader_console_init();
|
||||
#endif
|
||||
|
||||
led_puts("L1");
|
||||
|
||||
ret = initdata->dpll_init(bd);
|
||||
if (ret) {
|
||||
pr_err("failed to init DPLL\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
led_puts("L2");
|
||||
|
||||
ret = initdata->memconf_init(bd);
|
||||
if (ret) {
|
||||
pr_err("failed to init MEMCONF\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
led_puts("L3");
|
||||
|
||||
initdata->dram_clk_init();
|
||||
|
||||
led_puts("L4");
|
||||
|
||||
ret = initdata->umc_init(bd);
|
||||
if (ret) {
|
||||
pr_err("failed to init DRAM\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
led_puts("L5");
|
||||
}
|
||||
|
|
Loading…
Add table
Reference in a new issue