Drop the unneeded portnr function argument, the portnr is part of the
usb_device struct which is passed via the dev argument.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
The device-model usb_legacy_port_reset function calls the device-model
usb_port_reset function which is a 1 on 1 copy of the non dm
usb_legacy_port_reset and this is the only use of usb_port_reset in all
of u-boot.
Drop both, and alway use the usb_legacy_port_reset() version in
common/usb.c .
Also while at it make it static as it is only used in common/usb.c .
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Simon Glass <sjg@chromium.org>
As you see in driver/Makefile, Kbuild descends into the driver/core/
directory only when CONFIG_DM is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Currently, DM_FLAG_ACTIVATED is set twice; before calling
uclass_pre_probe_device() and again before calling drv->probe().
It looks like Simon's intention is the first one.
The DM_FLAG_ACTIVATED was moved twice, by commit 02eeb1bbb1
(dm: core: Mark device as active before calling its probe()
method), and then by commit 206d4d2b4b (dm: core: Mark device
as active before calling uclass probe() methods).
The first marking was added by the last move.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
The command "dm uclass" tries to display all the UClasses, but
some of them might be disabled by Kconfig.
The function do_dm_dump_uclass() iterates over all the UClass IDs
and calls uclass_get() for each of them. Then, it displays annoying
message "Cannot find uclass for id ..." every time it fails to get
the UClass.
As a result, we get much noisier log for the "dm uclass" command.
=> dm uclass
uclass 0: root
- * root_driver @ bfb54028, seq 0, (req -1)
Cannot find uclass for id 1: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 2: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 3: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 4: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 5: please add the UCLASS_DRIVER() ...
Cannot find uclass for id 6: please add the UCLASS_DRIVER() ...
This commit suppresses these warnings.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
This function can only handle a syscon device. It is possible that someone
will make a mistake, so add a check for this.
Also we should return -ENODEV when a device cannot be found, so update the
syscon_get_regmap_by_driver_data() to follow this convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
We normally use -ENODEV for a missing device, rather than -ENOENT. The
latter is reserved for when we have a device but cannot find something
within it.
Also avoid looking at the root LED device since it is only a container.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a test to confirm that we can probe this device. Since there is no
MMC stack support in sandbox at present, this is as far as the test goes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move sandbox over to use the reset uclass for reset, instead of a direct
call to do_reset(). This allows us to add tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add drivers for sandbox. One can only perform a warm reset (which does
nothing). The other can perform a cold reset or a power reset (the
latter will quit U-Boot). These can be used for testing the reset uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a new reset_walk_halt() function to cause a reset and then halt on
failure. The reset_walk() function returns an error code.
This is needed for testing since otherwise U-Boot will halt in the middle
of a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use the common function to obtain the number from the end of the string,
instead of a local function. Also tweak the position of a debug() statement.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.
Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.
Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.
To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Since Rockchip requires 32-bit serial access, add this to the driver.
Refactor a little to make this easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for a driver which sets up DRAM and can return information about
the amount of RAM available. This is a first step towards moving RAM init
to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is a common requirement to update some PMIC registers. Provide some
simple convenience functions to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
To reduce unnecessary code size in an uncommon code path, use debug()
where possible(). The driver returns an error which indicates failure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The device tree provides information about which regulators should be
on at boot, or always on. Use this to set them up automatically.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
The regulator_autoset() function mixes printf() output and PMIC adjustment
code. It provides a boolean to control the output. It is better to avoid
missing logic and output, and this permits a smaller SPL code size. So
split the output into a separate function.
Also rename the function to have a by_name() suffix, since we would like
to be able to pass a device when we know it, and thus avoid the name
search.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Decide when the regulator is set up whether we want to auto-set the voltage
or current. This avoids the complex logic spilling into the processing code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
This is not user input (i.e. from the command line). It should be possible
to get the case correct and avoid the case-insensitive match. This will
help avoid sloppy device tree setups.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Add basic support for MMC, providing a uclass which can set up an MMC
device. This allows MMC drivers to move to using driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass <sjg@chromium.org>
Many SoCs have a number of system controllers which are dealt with as a
group by a single driver. It is a pain to have to add lots of compatible
strings and/or separate drivers for each. Instead we can identify the
controllers by a number and request the address of the one we want.
Add a simple implementation of this which can be used by SoC driver code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a simple implementaton of register maps, supporting only direct I/O
for now. This can be enhanced later to support buses which have registers,
such as I2C, SPI and PCI.
It allows drivers which can operate with multiple buses to avoid dealing
with the particulars of register access on that bus.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function can be used for testing to manually request a GPIO for use,
without resorting to the legacy GPIO API.
Signed-off-by: Simon Glass <sjg@chromium.org>
In some rare cases it is useful to be able to locate a device given a device
tree node offset. An example is when you have an alias that points to a node
and you want to find the associated device. The device may be SPI, MMC or
something else, but you don't need to know the uclass to find it.
Add a function to do a global search for a device, given its device tree
offset.
Signed-off-by: Simon Glass <sjg@chromium.org>
To avoid bloating SPL code, use debug() where possible in the driver model
core code. The error code is already returned, and can be investigated as
needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
In SPL it is sometimes useful to be able to obtain a dump of the current
driver model state. Since commands are not available, provide a way to
directly call the functions to output this information.
Adjust the existing commands to use these functions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change infinite loop mechanism to timer based polling for QBMAN release in
ldpaa_eth_rx.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Polling of TX conf frames is not a mandatory option.
Packets can be transferred via WRIOP without TX conf frame.
Configure ldpaa_eth driver to use TX path without confirmation frame
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Volatile command does not return frame immidiately, need to wait till a frame
is available in DQRR. Ideally it should be a blocking call.
Add timeout handling for DQRR frame instead of retry counter.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Do not immediately return if the enqueue function returns -EBUSY; re-try
mulitple times.
if timeout occures, release the buffer.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree. Fixups are implemented for PCI controllers
initially.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
delete any existing ICID pools in the DPC and create
a new one based on the stream ID partitioning for
the SoC
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Stream IDs on ls2085a devices are not hardwired and are
programmed by sw. There are a limited number of stream IDs
available, and the partitioning of them is scenario dependent.
This header defines the partitioning between legacy, PCI,
and DPAA2 devices.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Management complex major version should match to the firmware present in flash.
Return error during mismatch of major version.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update qbman driver
- As per latest available qbman driver
- Use of atomic APIs
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Geoff Thorpe <Geoff.Thorpe@freescale.com>
CC: Haiying Wang <Haiying.Wang@freescale.com>
CC: Roy Pledge <Roy.Pledge@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update flibs changes to mc-0.6.0.1 for dpmang, dprc, dpni and dpio objects
Also rename qbman_portal_ce/ci_paddr to qbman_portal_ce/ci_offset in
dpio_attr. These are now offsets from the SoC QBMan portals base.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Flush buffer before releasing to BMan after TX_conf to ensure, the core does
not have any cachelines that the WRIOP will DMA to.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Make it easier for the user to notice when the MC firmware
had problems booting.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch fixes the DDR hide logic for LS2085a, correcting the way
the Debug Server FW and MC FW images are placed on the top of system
DDR and how the rest of the system DDR space is made visibile to Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
In case SPD address changes between board revisions, updating SPD
address can be called from board file.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Fix below build warnings on armv8,
drivers/spi/fsl_dspi.c: In function ‘fsl_dspi_ofdata_to_platdata’:
drivers/spi/fsl_dspi.c:667:2:
warning: format ‘%x’ expects argument of type ‘unsigned int’,
but argument 2 has type ‘fdt_addr_t’ [-Wformat=]
debug("DSPI: regs=0x%x, max-frequency=%d, endianess=%s, num-cs=%d\n",
^
lib/fdtdec.c: In function ‘fdtdec_get_addr_size’:
lib/fdtdec.c:105:4:
warning: format ‘%lx’ expects argument of type ‘long unsigned int’,
but argument 3 has type ‘fdt_size_t’ [-Wformat=]
debug("addr=%08lx, size=%08lx\n",
^
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Acked-by: Simon Glass <sjg@chromium.org>
We should not leave the expansion ROM address window open when there
is not a valid ROM.
Suggested-by: Matt Porter <mporter@konsulko.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Currently PCI expansion ROM address is assigned by a call to
pciauto_setup_rom() outside of the pci auto config process.
This does not work when expansion ROM is on a device behind
PCI bridge where bridge's memory limit register was already
programmed to a value that does not cover the newly assigned
expansion ROM address. To fix this, we should configure the
ROM address during the auto config process.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
This driver was originally added to support the native IDE mode for
Intel chipset, however it has some bugs like not supporting ATAPI
devices, endianness issue, or even broken build when CONFIG_LAB48.
Given no board is using this driver as of today, rather than fixing
all these issues we just remove it from the source tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The logic is incorrect and currently has no effect. Fix it so that we can
write to SPI flash, since by default it is write-protected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
The status register on ICH9 is a single byte, so use byte access when
writing to it, to avoid updating the control register also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Store VESA parameters to Linux setup header so that vesafb driver
in the kernel could work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit
color depth is configured. Since 24-bit mode already uses 4 bytes
internally, it should be OK to just add this option in switch case.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Per PCI spec, VGA device reports its class as standard 030000h in
its configuration space, so we can use it to determine if we need
run option rom instead of testing the supported vendor/device ids.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
so that sub-buses are numbered correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Only the PCI controller has access to the PCI region information. Make sure
to use the controller (rather than any attached bridges) when configuring
devices.
This corrects a failure to scan and configure devices when driver model is
enabled for PCI.
Also add a comment to explain the problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add driver model support to the mc146818 rtc driver. Also clean up
the driver a little bit for coding convention issues.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Introduce a new method 'get_count' in the UCLASS_CPU ops to get
the number of CPUs in the system.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see
if it is NULL. It should test against cpu_ops->get_info.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tidy up three minor problems in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Since commit 09c3280754 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.
=> nand read 80000000 10000 10000
NAND read: Offset exceeds device limit
=> nand erase 100000 100000
NAND erase: Offset exceeds device limit
The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This patch adds USB EHCI host support for the common mvebu platform.
Including the Armada 38x.
Tested on DB-88F6280-GP eval board.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch changes the initialization of the AHCI controller to not
enable the default interrupts (DEF_PORT_IRQ). As interrupts are
not used in U-Boot in general, this should not break the common AHCI
driver operation.
This change is needed to support the Marvell Armada 38x AHCI
controller. With interrupts enabled, this results in timeouts in
ahci_device_data_io(). Not enabling these interrupts fixes this
problem and the common AHCI driver works fine.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the
following problem occured. The SPL runs in internal SRAM which is
the L2 cache locked to memory. When the MMC buffers now are located
on the stack (or bss), the SDIO controller (SDHCI) can't write into
this L2 cache memory.
This patch introduces a method to use a fixed buffer that will be
used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER.
This way, the board can use this buffer address located in SDRAM
for all transfers. This solves this SPL problem on the A38x and
should only be used in the SPL U-Boot version.
Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
The loop counter based timeout detection does not work on the Armada
38x based board (DB-88F6820-GP). At least with dcache enabled a
timeout is detected. Without dcache enabled, the timeout does not
occur. Increasing the loop counter solves this issue. But a better
solution is to use a timer based timeout detection instead. This
patch now implements this timer based detection.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
When driver model is not used the current code does not correctly select
the pinmux for the I2C bus. This bug was introduced by this commit:
8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The temperature calculation must be typecasted to keep the compiler
from sign extending a negative value prior to division.
This fixes an issue where if the CPU temperature is <0C it will get stuck
in the busywait loop until the CPU heats up to 0C.
Cc: Ye Li <b37916@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four
I2C instances available in VF610.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
This locally defined struct is actually only used once
and as an opaque type. Remove it for clarity.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Remove the check for temperature being within the min/max range and enter the
busywait cooling loop whenever the CPU temperature is over the critical temp.
This fixes the issue where if a board was booted at a temp greater than
the CPU temperature max, it would skip the loop and never indicate or try
to address the overtemp issue.
Cc: Ye Li <b37916@freescale.com>
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
When compling under 64bit platforms, there are lots of warnings,
like:
drivers/block/ahci.c:114:18: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
^
drivers/block/ahci.c: In function ?.hci_host_init?.
drivers/block/ahci.c:218:49: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
......
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
commit f566c99 "net: Update hardware MAC address if it changes in env"
removes writing MAC address to designware controller after soft reset.
This makes designware ethernet port fail to work. Actually the MAC
address should always be programmed after soft reset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Added UART DCC support for armv8
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The LPC32XX GPIO driver platdata currently contains GPIO state information,
which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
This patch makes the code compatible with FIFO depths other than 4
bytes. It also simplify read/write FIFO loops.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
sram size could be different on different socs, e.g. on stv0991 it is 256 while
on altera platform it is 128. It is better to receive it from device tree.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Added TEGRA20_SLINK entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Added TEGRA20_SFLASH entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Added TEGRA114_SPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Added ICH_SPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Added FSL_QSPI entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Haikun Wang <haikun.wang@freescale.com>
DM supported spi drivers are enbled only when DM_SPI enabled,
so added DM_SPI if condition in Kconfig to show thoese only
when it enabled.
Also re-order the config items as incresing alphabetic order.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Added SPI_FLASH_DATAFLASH entry on Kconfig with help description.
data flash driver comes with good decription, hence moved the
same on to kconfig help decription.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Haikun Wang <haikun.wang@freescale.com>
Added SPI_FLASH_MTD entry on Kconfig with help description.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Rename CONFIG_SF_DATAFLASH into CONFIG_SPI_FLASH_DATAFLASH
as it follows the naming convention same as remaining configs.
Signed-off-by: Jagan Teki <jteki@openedev.com>
This patch includes asm/io.h for readl and writel calls.
build errors:
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe':
drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration]
drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer':
drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Michal Simek <michal.simek@xilinx.com>
This converts the xilinx spi driver to use the driver model.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz -> frequency
- req_hz -> freq
- base -> regs
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Arrange driver code in more readable format[1] for easy accessing
and readable.
[1] http://patchwork.ozlabs.org/patch/265683/
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Rex Chang <rchang@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Move the header code into driver for more readable and
easy to access it.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Rex Chang <rchang@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Move the header code into driver for more readable and
easy to access it.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Zap oc_tiny_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Zap ftssp010_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Axel Lin <axel.lin@ingics.com>
Zap andes_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Macpaul Lin <macpaul@andestech.com>
sst25wf040b doesn't support Auto Address Increment Programming command.
Remove SST_WR flag.
Signed-off-by: Haikun Wang <B53464@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Move common functions from cmd_nand.c (for calculating offset
and size from cmdline paramter) to common place, so they could
used from other commands which use mtd partitions.
For onenand the arg_off_size() is left in common/cmd_onenand.c.
It should use now the common arg_off() function, but as I could
not test onenand I let it there ...
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Add MTD layer driver for spi, original patch from:
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced
Changes from Heiko Schocher against this patch:
- Remove compile error if not defining CONFIG_SPI_FLASH_MTD:
LD drivers/mtd/spi/built-in.o
drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1
make: *** [drivers/mtd/spi] Fehler 2
- Add a README entry.
- Add correct writebufsize, to fit with Linux v3.14
MTD, UBI/UBIFS sync.
Note (From Jagan): For testing raw mtd parition erase/read/write operations
using cmd_sf, sf_mtd should be required to register the spi flash device to
MTD layer but the sf_mtd_info ops were not required until and unless if we
use any flash filesystem layer say for example UBI. Due to this the foot-print
got increased ~290bytes in non-UBI case here that should be acceptible.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Jagannadh Teki <jteki@openedev.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
=> sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 Bytes, total 264 KiB, revision d
=> sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
=> mw.l 82000000 45444342 20000
=> sf write 82000000 0 42000
SF: 270336 bytes @ 0x0 Written: OK
=> sf read 83000000 0 42000
SF: 270336 bytes @ 0x0 Read: OK
=> cmp.b 82000000 83000000 42000
Total of 270336 byte(s) were the same
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chakra Divi <cdivi@openedev.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This reverts commit f76eba38b3.
This patch did not have a full and proper copyright/S-o-b chain.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Conflicts:
include/configs/sun6i.h
include/configs/sun8i.h
This sets the default commands Kconfig to match
include/config_cmd_default.h commands in the common/Kconfig and removes
them from include/configs.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates]
Signed-off-by: Tom Rini <trini@konsulko.com>
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.
Remove the configs that behave this way from the archs.
A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:
SPIFLASH
DISPLAY_BOARDINFO
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
Patch 33fe2fb8df titled
"mmc: bcm283x: Remove get_timer_us() from mmc driver"
incorrectly replaced ad-hoc get_timer_us() function
with a plain get_timer(). The get_timer() operates in
mSec units instead of uSec though, which caused very
slow operation of the driver.
Restore the original behavior of the driver, but avoid
get_timer_us() and use timer_get_us() instead. The later
is part of the standard API.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jakub Kiciński <moorray3@wp.pl>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Jakub Kicinski <kubakici@wp.pl>
Without this we loose every other interrupt packet. We never noticed this
because with keyboards the packets which we were loosing would normally
be key release packets.
But now that we do keyrepeat in software instead of relying on the hid
idle functionality, missing a release will result in key repeat triggering.
This commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We want to see if the requested start or total block count are
unaligned. We discard the whole numbers and only care about the
remainder. Update the code to use div_u64_rem here and add a comment.
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Reported-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
commit c316f57 "mtd: OMAP: Enable GPMC prefetch mode" only enabled
prefetch mode for 8 bit nand access, this adds 16 bit as well.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
The prefech mode is a feature of the gpmc, not the ELM. An am3517
does not have an elm, but can do prefeches, so move the code out
of the CONFIG_NAND_OMAP_ELM ifdef.
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
Remove the unused sunxi_musb_exit method, there is no code in u-boot
calling the exit method, and our implementation was broken as it did
not disable the clocks and asserted reset.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Fully resetting the controller is a too big hammer, and the musb_core will
then afterwards fail to communicate with any endpoints other then 0 as
too much state was cleared.
Instead report vbus low for 200ms which will effectively end the current
session without needing to do a full reset.
This fixes usb mass-storage devices no longer working after a "usb reset"
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The AHCI driver currently waits 5s before timing out when sending a
data command to a drive. Some drives take upwards of 8s to respond to
the initial data command while they're spinning up. Increase the
data io timeout to 10s so that those drives can be found on initial
scsi scan.
Signed-off-by: Mark Langsdorf <mark.langsdorf@gmail.com>
Signed-off-by: Andre Przywara <osp@andrep.de>
