Commit graph

67 commits

Author SHA1 Message Date
Kumar Gala
39aaca1f66 ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms.  Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks.  We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
3c2a67eec8 ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms
the core not longer controls the enabling of the timebase.  We now need
to enable the boot core's timebase via CCSR register writes.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-24 12:05:29 -05:00
Kumar Gala
c348322ac7 ppc/85xx: Clean up do_reset
There is no reason to do a run time check for e500 v1 based cores to
determine if we have the GUTs RSTCR facility.  Only the first generation
of PQ3 parts (MPC8540/41/55/60) do not have it.  So checking to see if
we are e500 v2 would miss future parts (like e500mc).

Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 13:47:18 -05:00
Poonam Aggrwal
21170c80a8 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().
While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
58442dc01e ppc/85xx,86xx: Handling Unknown SOC version
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
0e870980a6 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Poonam Aggrwal
18bacc2027 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Peter Tyser
017f11f68e 8xxx: Break out DMA code to a common file
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-01 23:01:51 -05:00
Peter Tyser
2f21ce4d54 fsl/85xx, 86xx: Sync up DMA code
The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:58 -05:00
Peter Tyser
b1f12650d3 fsl: Create common fsl_dma.h for 85xx and 86xx cpus
Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:45 -05:00
Haiying Wang
8e55258f14 qe: Pass in uec_info struct through uec_initialize
The uec driver contains code to hard code configuration information for the uec
ethernet controllers. This patch creates an array of uec_info structures, which
are then parsed by the corresponding driver instance to determine configuration.
It also creates function uec_standard_init() to initialize all UEC interfaces
for 83xx and 85xx.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:17:02 -05:00
Haiying Wang
b3d7f20f43 85xx: Add QE clk support
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <Timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:16:59 -05:00
Kumar Gala
71b358cc26 85xx: Added MPC8535/E identifiers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:16:26 -05:00
Haiying Wang
22b6dbc169 MPC85xx: Add MPC8569 CPU support
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30 13:33:51 -05:00
Wolfgang Denk
1bba30efe1 Coding style cleanup, update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-02-19 00:41:08 +01:00
Andy Fleming
80522dc836 85xx: Add eSDHC support for 8536 DS
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16 18:07:43 -06:00
Srikanth Srinivasan
8d949aff38 mpc85xx: Add support for the P2020
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:55 -06:00
Kumar Gala
b29dee3c90 85xx: Format cpu freq printing to handle 8 cores
Only print 4 cpu freq per line.  This way when we have 8 cores its a
bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:50 -06:00
Haiying Wang
2fc7eb0cfc Add secondary CPUs processor frequency for e500 core
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS,
and prints each CPU's frequency separately. It also fixes up each CPU's
frequency in "clock-frequency" of fdt blob.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-23 17:03:14 -06:00
Trent Piepho
ada591d2a0 mpc8[56]xx: Put localbus clock in sysinfo and gd
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency
and print it out, but don't save it.

This changes where its calculated and stored to be more consistent with the
CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock.

The localbus frequency is added to sysinfo and calculated when sysinfo is
set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are.

get_clocks() copies the frequency into the global data, as the other
frequencies are, into a new field that is only enabled for MPC85xx and
MPC86xx.

checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency
from sysinfo, like the other frequencies, instead of calculating it on the
spot.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:49 -06:00
Trent Piepho
446c381e3e mpc8568: Double local bus clock divider
The clock divider for the MPC8568 local bus should be doubled, like the
other newer MPC85xx chips.

Since there are now more chips with a 2x divider than a 1x, and any new
85xx chips will probably be 2x, invert the sense of the #if so that it
lists the 1x chips instead of the 2x ones.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:32:48 -06:00
Trent Piepho
a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits
instead of four.

In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems.  It
should be safe as the fifth bit was defined as reserved and set to 0.

Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV.

Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19 18:20:25 -06:00
Ben Warren
0e8454e990 Moved initialization of QE Ethernet controller to cpu_eth_init()
Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:03 -08:00
Ben Warren
3456a14827 Moved initialization of FCC Ethernet controller to cpu_eth_init
Affected boards:
    Several MPC8xx boards
    Several MPC8260/MPC8272 boards
    Several MPC85xx boards

Removed initialization of the driver from net/eth.c

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:02 -08:00
Ben Warren
62e15b497f Fix typo in cpu/mpc85xx/cpu.c
CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09 21:38:02 -08:00
Kumar Gala
0f060c3bf8 85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:47 -05:00
Wolfgang Denk
08ef89ecd1 Use strmhz() to format clock frequencies
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 11:25:38 +02:00
Ed Swarthout
6856b3d022 85xx if NUM_CPUS>1, print cpu number
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18 21:54:05 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Jason Jin
c0391111c3 Fix the incorrect DDR clk freq reporting on 8536DS
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-10-07 15:37:08 -05:00
Sergei Poselenov
59f630588e Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-09-09 10:14:32 +02:00
Andy Fleming
75b9d4ae0d Pass in tsec_info struct through tsec_initialize
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Kumar Gala
ef50d6c06e mpc85xx: Add support for the MPC8536
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-08-27 11:43:54 -05:00
Kumar Gala
129ba616b3 mpc85xx: Add support for the MPC8572DS reference board
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-08-27 11:43:53 -05:00
Kim Phillips
06b4186c10 mpc85xx: use IS_E_PROCESSOR macro
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-07-14 17:01:34 -05:00
Wolfgang Denk
9692cab76f Merge branch 'master' of git://www.denx.de/git/u-boot-net 2008-07-09 23:22:54 +02:00
Ben Warren
dd35479a50 Add mechanisms for CPU and board-specific Ethernet initialization
This patch is the first step in cleaning up net/eth.c, by moving Ethernet
initialization to CPU or board-specific code.  Initial implementation is
only on the Freescale TSEC controller, but others will be added soon.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-07-06 00:20:59 -07:00
Wolfgang Denk
e093a24762 Coding Style Cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-06-28 23:34:37 +02:00
Anatolij Gustschin
96026d42fa Fix 4xx build issue
Building for 4xx doesn't work since commit 4dbdb768:

In file included from 4xx_pcie.c:28:
include/asm/processor.h:971: error: expected ')' before 'ver'
make[1]: *** [4xx_pcie.o] Error 1

This patch fixes the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 22:48:45 +02:00
Sergei Poselenov
740280e68c Added the upmconfig() function for 85xx.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-11 00:29:29 -05:00
Wolfgang Grandegger
6beecfbb54 MPC85xx: Beautify boot output of L2 cache configuration
The boot output is now aligned poperly with other boot output
lines, e.g.:

  FLASH: 128 MB
  L2:    512 KB enabled

Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
2008-06-10 18:22:26 -05:00
Kumar Gala
4dbdb7681e 85xx: expose cpu identification
The current cpu identification code is used just to return the name
of the processor at boot.  There are some other locations that the name
is useful (device tree setup).  Expose the functionality to other bits
of code.

Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out.  This is mainly to allow the most flexible use
of the name.  The device tree code tends to not care about the 'E' suffix.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-10 18:22:25 -05:00
Kumar Gala
ee1e35bede 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define it
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-09 13:31:20 -05:00
Sergei Poselenov
793670c3c0 Fixed reset for socrates
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-05-20 23:27:50 +02:00
Kumar Gala
022f121635 85xx: Round up frequency calculations to get reasonable output
eg. because of rounding error we can get 799Mhz instead of 800Mhz.

Introduced DIV_ROUND_UP and roundup taken from linux kernel.

Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-04-24 15:42:35 +02:00
James Yang
e9ea679918 85xx: Show DDR memory data rate in addition to the memory clock frequency.
Show the DDR memory data rate in addition to the memory clock
frequency.  For DDR/DDR2 memories the memory data rate is 2x the
memory clock.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
James Yang
591933ca6e 85xx: get_tbclk() speed up and rounding fix
Speed up get_tbclk() by referencing pre-computed bus clock
frequency value from global data instead of sys_info_t.  Fix
rounding of result to nearest; previously it was rounding
upwards.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26 11:43:04 -05:00
Andy Fleming
1ced121600 Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:04 -05:00
Kumar Gala
d435793229 Handle Asynchronous DDR clock on 85xx
The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.

Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00
Kumar Gala
04db400892 Stop using immap_t on 85xx
In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11 22:34:20 -06:00