Commit graph

49643 commits

Author SHA1 Message Date
Marek Vasut
68b83cb76b ARM: rmobile: Fix LBSC programming offset on M2 Porter
The offset of CSWCRx starts at 0x30, fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13 23:41:45 +02:00
Marek Vasut
27d7f04a47 ARM: rmobile: Enable SCIFA0 early on H2 Stout
The H2 Stout uses SCIFA0 for serial console, make sure it is
available very early on when probing from DT.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13 23:41:44 +02:00
Marek Vasut
451e22fa33 serial: sh: Add SCIFA0 address entry
Add the SCIFA0 address entry so it can be used in TPL if needed
due to size restrictions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13 23:41:44 +02:00
Marek Vasut
d526801bf4 net: sh_eth: Add remaining Gen2 DT compatible
Add compatible strings for R8A7790, R8A7793 and R8A7794, since the
contemporary DTs use those don't have a generic match value.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-04-13 23:41:44 +02:00
Marek Vasut
cc64a51546 clk: renesas: Minor clean up of the R8A7790 clock driver
The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks
is also not used in U-Boot, so drop it too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13 23:41:44 +02:00
Heinrich Schuchardt
901b77b9c8 vexpress: fix syntax error in armv7_boot_nonsec_default()
With CONFIG_ARMV7_BOOT_SEC_DEFAULT=y a syntax error occurs.
Add the missing semicolon.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-04-13 17:06:16 -04:00
Tom Rini
d291d8235b configs: Fixup some CPSW-related items
- For am335x_pdu001 we do not want the CPSW driver, drop it
- Re-sync the defconfig for am43xx_evm_rtconly as it came in after the
  patch that converted CPSW to Kconfig was posted but before it was
  applied.
- Drop empty section / comments from pengwyn
- Drop empty section / comments from baltos and drop unused
  CONFIG_SPL_NET_VCI_STRING (it does not enable CONFIG_SPL_NET_SUPPORT
  currently and SPL_NET_VCI_STRING has been migrated already).

Cc: Felix Brack <fb@ltec.ch>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Lothar Felten <lothar.felten@gmail.com>
Fixes: f02b8d1761 ("Migrate CONFIG_DRIVER_TI_CPSW to Kconfig")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Felix Brack <fb@ltec.ch>
Tested-by: Felix Brack <fb@ltec.ch>
2018-04-13 17:06:16 -04:00
Vasyl Vavrychuk
3194daa10b vxworks: fixed cpu enable using PSCI on armv8
Without armv8_setup_psci register VBAR_EL3 is not set up property which
makes SMC calls jump to invalid location.

smp_kick_all_cpus is required to make slave cpus leave gic_wait_for_interrupt.
Without this they will never pursue booting process.

Fix was applied to the two ways of booting VxWorks: bootvx and bootm commands.

This implementation is very similar to what is done in boot_jump_linux
in arch/arm/lib/bootm.c file.

Tested on VxWorks 7 release SR0520 2017-12-08 Intel Stratix 10 SX SoC
Development Kit board.

Signed-off-by: Vasyl Vavrychuk <vasyl.vavrychuk@globallogic.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-04-13 17:06:05 -04:00
Christian Gmeiner
52ff8020d0 kconfig: add CONFIG_CC_COVERAGE
Make it possible to use gcc code coverage analysis.

v1 -> v2:
 - Kconfig: remove not needed 'default n'
 - Makefile: use consistent spacing

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-04-13 13:02:50 -04:00
Jean-Jacques Hiblot
cd5d274252 configs: dra7xx_evm/dra7xx_hs_evm: Enable AHCI and PIPE3
Those options are required to enable support for SATA on DRA7 platforms.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-04-13 13:02:50 -04:00
Jean-Jacques Hiblot
64563f5333 dwc_ahci: Fix breakage
The dwc_ahci has been broken for quite some time now. The breakage has been
introduced by the series "dm: scsi: Enhance SCSI support for driver model"

Use ahci_bind_scsi() and ahci_probe_scsi() to properly bind and probe the
driver.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-04-13 13:02:50 -04:00
Tom Rini
93cb6142c1 Merge git://git.denx.de/u-boot-sh 2018-04-13 09:23:53 -04:00
Tom Rini
c8a0126f88 Merge git://git.denx.de/u-boot-usb 2018-04-13 09:22:56 -04:00
Marek Vasut
97ed677831 ARM: rmobile: Set maximum kernel size to 64 MiB on Gen3
The Gen3 kernel images are often above 8 MiB, increase the
maximum kernel size to 64 MiB to future-proof it, just like
many other ARM64 boards do.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:19:52 +02:00
Marek Vasut
7beccc52a1 ARM: rmobile: Fix the memory map on Gen3
Fix up the memory map on Gen3 to match datasheet properly.
This simplifies the memory map setup as well, since we do
no longer need this massive complexity.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:19:52 +02:00
Marek Vasut
ea5512eb09 spi: sh_qspi: Make use of the 32byte FIFO
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing
the SPI transmission 1 byte at time, if there is a 32byte chunk of
data to be transferred, fill the FIFO completely and then transfer
the data to/from the FIFO. This increases the SPI NOR access speed
significantly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11 23:19:51 +02:00
Marek Vasut
9573db654d spi: sh_qspi: Replace ad hoc waiting with wait_for_bit
Replace the ad-hoc endless loops with wait_for_bit() with
reasonable timeout. Note that the loops had internal 10uS
delays, although there is no reason for those on this HW,
so they are dropped.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11 23:19:51 +02:00
Marek Vasut
1182264952 spi: sh_qspi: Drop SPBDCR wait
Waiting for SPBDCR == 1 is not required and is covered by the
subsequent wait for SPSR_SPRFF, so drop this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11 23:19:51 +02:00
Marek Vasut
0e6fa20b14 spi: sh_qspi: Replace data types with short ones
Just replace unsigned {char,short,long} with u{8,16,32},
no functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2018-04-11 23:19:50 +02:00
Marek Vasut
fbebea27e1 mtd: spi: Add Renesas RPC SPI-flash driver
Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:12:01 +02:00
Marek Vasut
a405a55ba8 mtd: rpc: Add Renesas RPC Hyperflash driver
Add driver for the RPC block in Hyperflash mode. This driver allows
access to a CFI Hyperflash attached to the RPC block and does not
support RPC in SPI mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:12:00 +02:00
Marek Vasut
cf39f3f304 mmc: renesas-sdhi: Wait after reconfiguring pins
The IP requires some time to recuperate after the IO pin
properties were changed. Add a delay to assure this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:12:00 +02:00
Marek Vasut
5ee7c9dc77 mmc: matsushita-common: Add missing else
Fix minor rebase omission, the else was missing which triggered
two accesses to the register on 64bit variant of the IP.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:12:00 +02:00
Marek Vasut
f23b208ebe mmc: matsushita-common: Wait for command completion
Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:12:00 +02:00
Marek Vasut
8dc9a10e49 mmc: matsushita-common: Correctly set mode in 16bit
The HOST_MODE register must be set to 0 when the IP is operated in 16bit
mode, otherwise 16bit access to the data FIFO may fail.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:12:00 +02:00
Marek Vasut
01c0151a36 mmc: matsushita-common: Special case only select registers in 16bit
There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:59 +02:00
Marek Vasut
8af6737d45 ARM: rmobile: Enable HS200 mode on RCar Gen3
Enable the HS200 on RCar Gen3 platforms, since the SDHI core supports it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:11:59 +02:00
Marek Vasut
f63968ba26 mmc: renesas-sdhi: Add Renesas SDR104/HS200 tuning support
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:59 +02:00
Marek Vasut
0e2bd5aa49 mmc: matsushita-common: Export register access functions
Export the matsu_sd_{read,write}l() common register access
functions, so that they can be used by other drivers sharing
the common code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:59 +02:00
Marek Vasut
e10422f108 mmc: matsushita-common: Properly handle pin voltage configuration
Factor out the regulator handling into set_ios and add support for
selecting pin configuration based on the voltage to support UHS modes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:59 +02:00
Marek Vasut
58c35b17aa mmc: matsushita-common: Always check controller version
Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:59 +02:00
Marek Vasut
a7b7401c78 mmc: matsushita-common: Handle bus width 0
Handle bus width 0 as 1-bit bus to assure valid content of
MATSU_SD_OPTION register WIDTH field.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:58 +02:00
Marek Vasut
635ae6fefa mmc: matsushita-common: Handle DMA completion flag differences
The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:58 +02:00
Marek Vasut
78773f1467 mmc: matsushita-common: Handle Renesas div-by-1
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:58 +02:00
Marek Vasut
f98833dbe6 mmc: matsushita-common: Add Renesas RCar quirks
Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:58 +02:00
Marek Vasut
147169d9c9 mmc: matsushita-common: Use mmc_of_parse()
Drop the ad-hoc DT caps parsing in favor of common framework function.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:58 +02:00
Marek Vasut
7cf7ef81ed mmc: renesas-sdhi: Handle 16bit IP
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:57 +02:00
Marek Vasut
c769e60990 mmc: uniphier: Allow passing quirks to the probe function
Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:57 +02:00
Marek Vasut
db1266d696 mmc: uniphier: Add support for 16bit variant
Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:57 +02:00
Marek Vasut
620fd85c0b mmc: uniphier: Drop useless check
Drop useless check in matsu_sd_{read,write}q(), this is only ever
called to read the data from FIFO and only when 64bit variant of
the block is used anyway.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:57 +02:00
Marek Vasut
12a510e23f mmc: uniphier: Factor out FIFO accessors
Add macros to generate the FIFO accessors, since the code is almost
the same with only minor differences. This is done in preparation
for adding 16bit variant of the IP.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:56 +02:00
Marek Vasut
33f65ec83e ARM: rmobile: Switch to CONFIG_RENESAS_SDHI
Since the Renesas SDHI has it's own custom driver sharing the
common code with Uniphier one, adjust the Kconfig entries.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:56 +02:00
Marek Vasut
7dfddc099d mmc: renesas-sdhi: Add Renesas SDHI Kconfig entry
Add Kconfig entry for the Renesas SDHI variant of the controller
and split the Makefile entries accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:56 +02:00
Marek Vasut
e94cad93b7 mmc: uniphier: Split out SoC specific bits from the driver
Factor out common code from the uniphier SD driver, change the prefix
of the functions from uniphier_sd_ to matsu_sd_ and create separate
renesas-sdhi.c driver. Thus far, all the code is still compiled when
CONFIG_UNIPHIER_MMC is selected and there is no functional change.
This patch is a preparation for further split of the SoC specific
parts of the Matsushita SD driver, used both on Uniphier and R-Car.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-11 23:11:56 +02:00
Marek Vasut
78bf3f2180 ARM: rmobile: Enable HUSH on M2 Porter
Enable the HUSH shell, since it is far more capable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:11:55 +02:00
Marek Vasut
82239aa7cd ARM: rmobile: Add JTAG recovery support for M2 Porter
Add JTAG recovery support into the M2 Porter TPL. This allows the
TPL to be loaded over JTAG, initialize the system, wait for the
JTAG debugger to load U-Boot image into RAM and then resume and
start U-Boot from RAM.

The procedure is as follows:
1) Load u-boot-tpl.bin to 0xe6300000
2) Write magic number 0x1337c0de to 0xe6300020
   TPL checks for this particular magic and starts JTAG recovery
   if this number is present. This is not present by default.
3) Start U-Boot TPL from 0xe6300000
4) Wait for a message from TPL on UART indicating JTAG boot:
   "JTAG boot detected!"
5) Halt the system in JTAG debugger
6) Load U-Boot image (u-boot.img) to 0x4fffffc0
7) Write magic number 0xb33fc0de to 0xe6300024
   TPL checks for this particular magic to verify that the U-Boot
   image was loaded into DRAM by the JTAG debugger.
8) Resume the system in JTAG debugger

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:11:55 +02:00
Marek Vasut
9a5483e9df ARM: rmobile: Add TPL support on R8A7791 M2 Porter
Add and enable TPL on M2 Porter. The TPL must fit into 16 kiB due
to the Gen2 BootROM restriction. The TPL is running from MERAM and
is capable of performing the initial initialization of PFC, Clock,
GPIO, LBSC, DBSC and QSPI NOR. DBSC is responsible for bringing up
the DDR DRAM access. The TPL is capable of loading the next stage,
U-Boot, from either SPI NOR or UART as a fallback. If either does
provide a valid U-Boot uImage, the system stops, which allows the
operator to load U-Boot ie. via JTAG and start it manually.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:11:55 +02:00
Marek Vasut
c670607331 ARM: rmobile: Do not init caches in TPL before DRAM
Skip the cache initialization, which can be done later on in U-Boot
proper, since this interferes with early DRAM initialization in TPL.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:11:54 +02:00
Marek Vasut
ce19d4ca7d ARM: rmobile: Split U-Boot and SPL sources on Porter
Pull the SPL code from porter.c into a separate file in
preparation for the addition of system initialization code.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-11 23:11:54 +02:00
Tom Rini
1a7cdb88f5 Merge git://git.denx.de/u-boot-i2c 2018-04-11 17:00:52 -04:00