Commit graph

426 commits

Author SHA1 Message Date
Sriram Dash
0d7f1ae0fe armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2C
I2C code is put under CONFIG_SYS_I2C.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:45:27 -07:00
Sriram Dash
e45ff0ce63 armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC
IFC code is put under CONFIG_FSL_IFC

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:45:17 -07:00
Ashish Kumar
bdbcb52256 armv8: fsl-layerscape: Put SATA code under SATA configs
It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22 12:41:24 -07:00
Bin Meng
723b43daec blk: Remove various places that do flush cache after read
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.

The underlying drivers should be responsible for the cache operation.
Remove these codes completely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
2017-09-15 08:05:10 -04:00
York Sun
42f43aa258 armv8: fsl-layerscape: Add back L3 flushing for all exception levels
CCN-504 HPF registers were believed to be accessible only from EL3.
However, recent tests proved otherwise. Remove checking for exception
level to re-enable L3 cache flushing for all levels.

Signed-off-by: York Sun <york.sun@nxp.com>
Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-11 08:02:13 -07:00
York Sun
e9303a4146 armv8: fsl-layerscape: Fix MC reserved memory calculation
In case high region memory doesn't have enough space for Management
Complex (MC), the return value should indicate a failure so the
caller can handle it accordingly.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-11 08:01:07 -07:00
Ran Wang
15d59b5316 armv8: Add workaround for USB erratum A-009007
Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
9d1cd910f7 armv8: Add workaround for USB erratum A-008997
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter
settings

Change config of transmitter signal swings by setting register
PCSTXSWINGFULL to 0x47 to pass compliance tests.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
2a8a353958 armv8: Add workaround for USB erratum A-009798
The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE
to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ran Wang
2ab1553f08 armv8: Add workaround for USB erratum A-009008
USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXREFTUNE value to 0x9 is observed, change
set the same value.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:06 -07:00
Ashish Kumar
17d066fc5d armv8: fsl-layerscape: Support to add RGMII for ls1088aqds
This patch adds support for RGMII protocol

NXP's LDPAA2 support RGMII protocol. LS1088A is the
first Soc supporting both RGMII and SGMII.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
7769776a60 armv8: ls1088aqds: Add support of LS1088AQDS
This patch add support of LS1088AQDS platform.

The LS1088A QorIQTM Development System (QDS) is a high-performance
computing, evaluation, and development platform that supports the
LS1088A QorIQ Architecture processor.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:01:05 -07:00
Ashish Kumar
e84a324ba7 armv8: ls1088ardb: Add support for LS1088ARDB platform
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin
platform that supports the LS1088A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Disabled NAND in board header file]
Reviewed-by: York Sun <york.sun@nxp.com>

WIP: disable NAND for LS1088ARDB
2017-09-11 08:00:13 -07:00
Ashish Kumar
6d9b82d085 armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Ran Wang
5436c6a347 armv8: fsl: Use correct conditional compile for ls1012a
According current code base, CONFIG_LS1012A should be
CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be
wrongly called to disable all dwc3 USB nodes on LS1012A, which
cause Linux USB function stop working at all.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 08:00:13 -07:00
Ashish Kumar
c055cee195 armv8: fsl-lsch3: Make CCN-504 related code conditional
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs
in LSCH3 family may have differnt interconnect.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Udit Agarwal
15e7c681e1 LS2080ARDB: QSPI boot: Secure Boot image validation
Adds header address for PPA to be validated during ESBC phase for
ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It
must be initialized before the PPA.

Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Sumit Garg
06fb06f66c SECURE_BOOT: Unify memory map for Layerscape based platforms
Unify memory map for Layerscape based platforms. This patch includes
changes in bootscript, bootscript header and PPA header addresses
change as per unified memory map.

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Ashish Kumar
63b2316c5c fsl-layerscape: Consolidate registers space defination for CCI-400 bus
CoreLink Cache Coherent Interconnect (CCI) provides full cache
coherency between two clusters of multi-core CPUs and I/O coherency
for devices and I/O masters.

This patch add new config option SYS_FSL_HAS_CCI400 and moves
existing register space definaton of CCI-400 bus to fsl_immap to be
shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
in Kconfig.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[YS: revised commit message, squashed patches for armv8 and armv7]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11 07:55:36 -07:00
Ruchika Gupta
a797f274d7 ARMv8/sec_firmware : Update chosen/kaslr-seed with random number
kASLR support in kernel requires a random number to be passed via
chosen/kaslr-seed propert. sec_firmware generates this random seed
which can then be passed in the device tree node.

sec_firmware reserves JR3 for it's own usage. Node for JR3 is
removed from device-tree.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2017-08-26 14:56:11 -04:00
Simon Glass
00caae6d47 env: Rename getenv/_f() to env_get()
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.

Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.

Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-16 08:30:24 -04:00
Philipp Tomsich
b529993e02 spl: add hierarchical defaults for SPL_LDSCRIPT
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config
node), all the lingering definitions in header files will cause
warnings/errors due to the redefinition of the configuration item.

As we don't want to pollute the defconfig files (and values should
usually be identical for entire architectures), the defaults are moved
into Kconfig.  Kconfig will always pick the first default that
matches, so please keep these values at the end of each file (to allow
any board-specific Kconfig, which will be included earlier) to
override with an unconditional default setting.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:37 +02:00
Philipp Tomsich
e9e5d9d29f dm: timer: normalise SPL and TPL support
To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
  decision for each stage and under control of $(SPL_TPL_)TIMER
  instead of having the two-level configuration with TIMER and
  $(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
  not be compiled in

This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:36 +02:00
Philipp Tomsich
e6a0586277 armv8: move low-level assembly functions into function-sections
TPL builds today don't need to call into firmware or set up the MMU
(if this changes, it should be controlled through a config option
whether to include this or not), but include the needed support code
for this anyway.  By moving these unused low-level functions into
seperate function-sections, the linker can garbage-collect the unused
sections.

Note that (if DM support is enabled), there will be a call to the
cache-flushing code from alloc_priv(...) in drivers/core/device.c.
This then add 52 bytes of binary size (an increase from 20589 to 20641
bytes) compared to completely removing this code.

Even for a feature-rich TPL (including DM support as for the RK3368),
this equates to a size difference of significantly more than 10% in
TPL binary size.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:21 +02:00
Simon Glass
6500ec7a5a Convert CONFIG_CMD_PCI to Kconfig
This converts the following to Kconfig:
   CONFIG_CMD_PCI

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-11 15:41:50 -04:00
Hou Zhiqiang
bf7aecce04 armv8/fsl-lsch2: correct the config description of DSPI clock divider
It is derived from Platform clock instead of Platform PLL frequency.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-09 09:57:32 -07:00
Tom Rini
fe84c48eeb Xilinx changes for v2017.09
Zynq:
 - Add Z-Turn board support
 
 fpga:
 - Remove intermediate buffer from code
 
 Zynqmp:
 - dts cleanup
 - change psu_init handling
 - Add options to get silicon version
 - Fix time handling
 - Map OCM/TCM via MMU
 - Add new clock driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlmBs2kACgkQykllyylKDCFUGgCgmfop8Ki5+6QI7XQRP7u8nhjw
 KakAn1sYIRDFQ34AoxmiYa6RTmjepLMv
 =1Gh3
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2017.09

Zynq:
- Add Z-Turn board support

fpga:
- Remove intermediate buffer from code

Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver
2017-08-04 07:23:32 -04:00
Michal Simek
fd1b635c06 arm64: zynqmp: Add Kconfig option for adding psu_init to binary
There is a need to include psu_init also in mini u-boot configuration
that's why handle psu_init via Kconfig property.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Michal Simek
55de09292f arm64: zynqmp: Call psu_init from board_early_init_f
For some mini platforms there could be a need to include psu_init.
That's why move it to board file instead of spl only file.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
cb186e74fb arm64: zynqmp: Remove ifdef around zynqmp mmio read and write rotuines
This patch removes ifdef around mmio read and write rotuines
and make them a single routine by checking the current el.
This patch helps to remove ifdef around invoke_smc as well.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
a076789efe arm64: zynqmp: Define a way to intialize TCM
TCM on ZynqMP needs to be intialized in a sequence
and this patch provides a global routine to perform
this as per requirement.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Siva Durga Prasad Paladugu
189bec47ab arm64: zynqmp: Provide a Kconfig option to define OCM and TCM in MMU
This patch provides an option to include OCM and TCM memory
into MMU table with corresponding memory attributes.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-08-02 09:11:52 +02:00
Alison Wang
020b3ce8ae armv8: Remove duplicate definition for IH_ARCH_ARM and IH_ARCH_ARM64
The duplicate definitions for IH_ARCH_ARM and IH_ARCH_ARM64 are removed.
The definitions in <image.h> are used.

According to this modification, the comparison between os arch and cpu
arch is done in C programming instead of ASM programming.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Grygorii Strashko
8a049dd642 armv8: fsl-layerscape: use get_nand_dev_by_index()
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11 22:41:53 -04:00
Simon Glass
8eab1a58dd dm: scsi: Document and rename the scsi_scan() parameter
The 'mode' parameter is actually a flag to determine whether to display
a list of devices found during the scan. Rename it to reflect this, add a
function comment and adjust callers to use a boolean.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Simon Glass
fedb428c5b Convert CONFIG_SCSI to Kconfig
This converts the following to Kconfig:
   CONFIG_SCSI

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11 10:08:19 -06:00
Rob Clark
8bf5c1e191 arm64: use psci reset on snapdragon
This actually works on snapdragon.. not sure why we weren't using it.
Fixes reboot/poweroff when using UEFI.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2017-07-06 16:17:13 -04:00
Michal Simek
fb4000e871 arm64: zynqmp: Check pmufw version
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:42:13 +02:00
Siva Durga Prasad Paladugu
e0752bc184 arm64: zynqmp: Define routines for mmio write and read
Define routines of mmio write and read functionalities
for zynqmp platform.

Also do not call SMC from SPL because SPL is running before ATF in EL3
that's why SMCs can't be called because there is nothing to call.
zynqmp_mmio*() are doing direct read/write accesses and this patch does
the same. PMUFW is up and running at this time and there is a way to talk
to pmufw via IPI but there is no reason to implement IPI stuff in SPL if
we need just simple read for getting clock driver to work.

Also make invoke_smc as global so that it can be reused in
multile places where ever possible.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:42:06 +02:00
Michal Simek
6a1d91be31 arm64: zynqmp: Do not map unused OCM/TCM region
When OCM or TCM is protected this mapping still exist and it is causing access
violation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:40:58 +02:00
Michal Simek
b0259c840e arm64: zynqmp: Add comment about level shifter mode v1
Silicon v1 didn't support SD boot mode with level shifter.
Because system can't boot any error message is not shown
that's why comment is just a record if someone tries to debug it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-20 16:40:58 +02:00
Jean-Francois Dagenais
8bf62ae7da arm64: zynqmp: spl: use given boot_device instead of fetching it again
The boot_device argument to spl_boot_mode was massively added without
actually modifying the existing functions.

This commit actually makes use of the handed value, which is the same.

Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-19 16:53:10 +02:00
Jean-Francois Dagenais
e3fdf5d056 arm64: zynqmp: spl: fix dual SD controller support
When enabling both SDHCI controllers, spl_mmc.c would actually choose
device sdhci0 even if booted from sdhci1 (boot_device). This is because
spl_mmc_get_device_index(boot_device) expects BOOT_DEVICE_MMC2[_2] in
order to return index 1 instead of 0.

The #if defined(...) statement is copied from board/xilinx/zynqmp/zynqmp.c

So the key to properly enabling both controllers as boot sources is
defining both CONFIG_ZYNQ_SDHCI0 and CONFIG_ZYNQ_SDHCI1 in your board's
include/configs/*.h.

Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-19 16:53:09 +02:00
Michal Simek
bd89fba202 arm64: zynqmp: Wire SD1 level shifter mode to SPL
Add missing SD boot mode to SPL. zcu102-rev1.0 is supporting
this boot mode.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-19 16:53:09 +02:00
Michal Simek
439edf6120 arm64: Add NOLOAD attribute NOLOAD to .bss sections
Mark explicitly bss sections to not be loaded at
run time.
The similar patch was done in past by:
"Fix linker scripts: add NOLOAD atribute to .bss/.sbss sections"
(sha1: 64134f0112)

The problem is related to latest toolchain added to Xilinx
v2017.1 design tools where jtag loader is trying to access
ununitialized memory.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-06-05 14:13:12 -04:00
Michal Simek
3c85417f45 ARMv8: Add support for poweroff via PSCI
Add support for calling poweroff in case of psci is wired.
Based on the same solution as is used for reset.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Move all logic in to fwcall.c as other ARMs implement poweroff
via PMIC]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05 14:13:12 -04:00
Simon Glass
6e2941d787 common: freescale: Move arch-specific declarations
The declarations should not be in common.h. Move them to the arch-specific
headers.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-05 12:30:55 -04:00
Tom Rini
541f538f4c Merge git://git.denx.de/u-boot-fsl-qoriq 2017-06-03 18:05:04 -04:00
York Sun
8e59778bec armv8: layerscape: Enabling loading PPA during SPL stage
Loading PPA in SPL puts the rest of U-Boot (including RAM version
loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded,
PSCI is available.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-06-01 19:57:24 -07:00
York Sun
399e2bb60c armv8: layerscape: Make U-Boot EL2 safe
When U-Boot boots from EL2, skip some lowlevel init code requiring
EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These
initialization tasks are carried out before U-Boot runs. This applies
to the RAM version image used for SPL boot if PPA is loaded first.

Signed-off-by: York Sun <york.sun@nxp.com>
2017-06-01 19:57:24 -07:00