Commit graph

124 commits

Author SHA1 Message Date
Kever Yang
045029cbd1 rockchip: rk322x: add clock driver
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed format specified (%x -> %p) in clk_rk322x.c:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:45 +02:00
Tom Rini
524b42bc2c Merge git://git.denx.de/u-boot-uniphier
- fix sparse warnings
- sync DT with Linux
- add new board support (LD11/LD20 global)
2017-06-24 18:18:41 -04:00
Masahiro Yamada
1d21e1b97c ARM: uniphier: fix various sparse warnings
Fix warnings reported by sparse:
 - ... was not declared. Should it be static?"
 - cast to restricted __be32

While fixing those, the type conflict of cci500_init() was found.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-25 06:06:09 +09:00
Tom Rini
7df4ff2c26 Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-06-23 11:02:21 -04:00
Kever Yang
6a464d9cab rockchip: clk: rk3036: correct setting for pll integer mode
According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-06-23 16:40:23 +02:00
Tom Rini
872faf5d13 clk_rv1108.c: Fix unused variable warning
The variables gpll_init_cfg and apll_init_cfg are unused in this file,
remove them.

Cc: Simon Glass <sjg@chromium.org>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-23 10:38:05 -04:00
Simon Glass
d3cb46aa8c rockchip: Init clocks again when chain-loading
Detect with a previous boot loader has already set up the clocks and set
them up again so that U-Boot gets what it expects.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:45:33 -06:00
Simon Glass
b223c1aead rockchip: rk3288: Convert clock driver to use shifted masks
Shifted masks are the standard approach with rockchip since it allows
use of the mask without shifting it each time. Update the definitions and
the driver to match.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:45:33 -06:00
Andy Yan
bae2f282a9 rockchip: clk: Add rv1108 clock driver
Add clock driver support for Rockchip rv1108 soc

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:25 -06:00
Kever Yang
1960b01034 rockchip: clock: rk3036: some fix according TRM
- hclk/pclk_div range should use '<=' instead of '<'
- use GPLL for pd_bus clock source
- pd_bus HCLK/PCLK clock rate should not bigger than ACLK

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Kever Yang
37943aaeea rockchip: rk3036: clean mask definition for cru reg
Embeded the shift in mask MACRO definition in cru header file
and clock driver.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:20 -06:00
Andy Yan
d1dcf8527e rockchip: rk3368: Add clock driver
Add driver to setup the various PLLs and peripheral
clocks on the RK3368.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-06-07 07:29:19 -06:00
Simon Glass
8b92e1cd59 dm: clk: fixed: Update to support livetree
Update the fixed-rate clock driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:14 -06:00
Simon Glass
aa9bb0944a dm: clk: Update uclass to support livetree
Update the clk uclass to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:14 -06:00
Simon Glass
a4e0ef50da clk: Modify xlate() method for livetree
Update the xlate() method to use ofnode_phandle_args instead of the fdtdec
variant. This will allow drivers to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:14 -06:00
Simon Glass
45a26867e8 dm: core: Update device_bind_driver_to_node() to use ofnode
Adjust this function to us an ofnode instead of an offset, so it can be
used with livetree. This involves updating all callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:08 -06:00
Simon Glass
da409ccc4a dm: core: Replace of_offset with accessor (part 2)
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:04 -06:00
Simon Glass
a821c4af79 dm: Rename dev_addr..() functions
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:01 -06:00
Simon Glass
9d922450aa dm: Use dm.h header when driver mode is used
This header includes things that are needed to make driver build. Adjust
existing users to include that always, even if other dm/ includes are
present

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 06:57:52 -06:00
Tom Rini
1f5541c881 Merge git://git.denx.de/u-boot-rockchip
This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.
2017-05-10 17:40:11 -04:00
Philipp Tomsich
ffc1fac549 rockchip: clk: rk3399: allow requests for HDMI clocks
This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF,
which are clock gates in the HDMI output path for the RK3399.

As these are enabled by default (i.e. after reset), we don't implement
any logic to actively open/close these clock gates and simply assume
that their reset-default has not been changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
a70feb4620 rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS
The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS.
To allow us to add a efuse-driver (and more importantly, to allow
probes of such a driver to succeed), we need need to accept requests
for PCLK_EFUSE1024NS and return a non-error result.

As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't
implement any logic to manage this clock gate and simply assume that
the reset-default has not been changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
998c61ae60 rockchip: clk: rk3399: adapt MMC clk configuration to the updated RK3399 DTS
The clocking of the designware MMC controller in the upstream
(i.e. Linux) RK3399 has changed/does not match what the current DTS in
U-Boot uses: the first clock entry now is HCLK_SDMMC instead of
SCLK_SDMMC.

With the simple clock driver used for the RK3399, this needs a change
in the selector understood by the various case statements in the driver
to ensure that the driver still loads successfully.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
beb90a53f3 rockchip: clk: rk3399: fix off-by one during rate calculation in i2c/spi_set_rate
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
which had been mindlessly following the template of the i2c_set_rate
implementation) miscalculates the rate returned due to a off-by-one
error resulting from the following sequence of events:
  1. calculates 'src_div := src_freq / target_freq'
  2. stores 'src_div - 1' into the register (the actual divider applied
     in hardware is biased by adding 1)
  3. returns the result of the DIV_RATE(src_freq, src_div) macro, which
     expects the (decremented) divider from the hardware-register and
     implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)')

This can be observed with the SPI driver, which sets a rate of 99MHz
based on the GPLL frequency of 594MHz: the hardware generates a clock
of 99MHz (src_div is 6, the bitfield in the register correctly reads 5),
but reports a frequency of 84MHz (594 / 7) on return.

To fix, we have two options:
 * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't
   make for a particularily nice read
 * we simply call the i2c/spi_get_rate function (introducing additional
   overhead for the additional register-read), which reads the divider
   from the register and then passes it through the DIV_RATE macro

Given that this code is not time-critical, the more readable solution
(i.e. calling the appropriate get_rate function) is implemented in this
change.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
8fa6979beb rockchip: clk: rk3399: add clock support for SCLK_SPI1 and SCLK_SPI5
This change adds support for configuring the module clocks for SPI1 and
SPI5 from the 594MHz GPLL.

Note that the driver (rk_spi.c) always sets this to 99MHz, but the
implemented functionality is more general and will also support
different clock configurations.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
85c91cb694 rockchip: clk: rk3328: add ciu_clk entry for eMMC/SDMMC
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
45112271ef rockchip: clk: rk3288: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
7a25a63c13 rockchip: clk: rk3188: add ciu_clk entry for eMMC/SDMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for
it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Xu Ziyuan
7f0cfe478b rockchip: clk: rk3036: add ciu_clk entry for eMMC/SDIO
The genunie bus clock is sclk_x for eMMC/SDIO, add support for it.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Álvaro Fernández Rojas
5357eb95c0 dm: clk: add BCM6345 clock driver
This is a simplified version of linux/arch/mips/bcm63xx/clk.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Wenyou Yang
3fea809b42 clk: at91: Align the at91 pmc's compatibles
Align the at91 pmc's compatibles with kernel.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
a9513d47dc clk: at91: Align clk-master compatibles with kernel
Add the compatible "atmel,at91rm9200-clk-master" to align with
the kernel.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
bb1adf2943 clk: at91: Enhance the peripheral clock
Enhance the peripheral clock to support both at9sam9x5's and
at91rm9200's peripheral clock via the different compatibles.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
maxims@google.com
defb184904 aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:35 -04:00
maxims@google.com
3b95902d47 aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.

The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.

The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.

So, the network driver would only need to enable these clocks, no need
to configure the rate.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:35 -04:00
maxims@google.com
4999bb06cc aspeed: Add P-Bus clock in ast2500 clock driver
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:34 -04:00
maxims@google.com
413353b30b aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:31 -04:00
Vikas Manocha
280057bd7d stm32f7: use stm32f7 gpio driver supporting driver model
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:21 -04:00
Philipp Tomsich
ba3bf3879e rockchip: clk: rk3399: 24MHz is not a power of 2
The clock driver for the RK3399 mistakenly used (24 * 2^20) where it
should have used (24 * 10^6) in a few calculations.

This commits fixes this.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Philipp Tomsich
65d833038e rockchip: clk: rk3399: add clocking support for Ethernet
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock
is ungated through a call to clk_set_rate(...). Even though nothing
needs to be done on the RK3399 (the clock gates are open and the clock
is external), we need to implement enough support to at least return
success to enable driver probing.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Philipp Tomsich
61dff33b52 rockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPL
Due to differences in the code paths for SPL and non-SPL, some static
constant structures remain unused in each build variant. This raises
warnings with recent GCC versions (we currently use GCC-6.3).

The warnings addressed in this commit (by matching #if conditions for
the variable definition with their uses) are:

* for the SPL build:
    drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
                                 ^~~~~~~~~~~~~
    drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~
* for the non-SPL build:
    drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=]
     static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
                                 ^~~~~~~~~~~~~

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Heiko Stübner
f785357073 rockchip: clk: rk3188: Allow configuration of the armclk
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
startup take a lot of time. We therefore want to at least move to the safe
600MHz value we can use with default pmic settings.
This is also the freqency the proprietary sdram-init leaves the cpu at.

For boards that have pmic control later in u-boot, we also add the option
to set the maximum frequency of 1.6GHz, if they so desire.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:01:57 -06:00
Tom Rini
f9515756b6 Merge git://git.denx.de/u-boot-rockchip
This includes support for rk3188 from Heiko Stübner and and rk3328 from
Kever Yang.  Also included is SPL support for rk3399 and a fix for
rk3288 to get it booting again (spl_early_init()).
2017-03-17 14:15:17 -04:00
Vikas Manocha
b5be8f5ea8 stm32f7: clk: remove usart1 clock enable from board init
Before clock driver availability it was required to enable usart1 clock
for serial init but now with clock driver is taking care of usart1 clock.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2017-03-17 14:15:14 -04:00
Vikas Manocha
712f99a5dd clk: stm32f7: add clock driver for stm32f7 family
add basic clock driver support for stm32f7 to enable clocks required by
the peripherals.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-17 14:15:12 -04:00
Kever Yang
41793000d7 rockchip: rk3328: add clock driver
Add rk3328 clock driver and cru structure definition.

Signed-off-by: William Zhang <william.zhang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:46 -06:00
Heiko Stübner
dcdd32788a rockchip: rk3188: Add clock driver
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:45 -06:00
Heiko Stübner
6496498a62 rockchip: clk: rk3288: limit gpll and cpll init to SPL build
The gpll and cpll init values are only used in rk_clk_init in the SPL
and therefore produce compile time warnings in regular uboot builds.
Fix that with an #ifdef.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Simon Glass <sjg@chromium.org>
Added rockchip tag:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:44 -06:00
Heiko Stübner
27326c7ee2 dm: allow limiting pre-reloc markings to spl or tpl
Right now the u-boot,dm-pre-reloc flag will make each marked node
always appear in both spl and tpl. But systems needing an additional
tpl might have special constraints for each, like the spl needing to
be very tiny.

So introduce two additional flags to mark nodes for only spl or tpl
environments and introduce a function dm_fdt_pre_reloc to automate
the necessary checks in code instances checking for pre-relocation
flags.

The behaviour of the original flag stays untouched and still marks
a node for both spl and tpl.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2017-03-16 16:03:44 -06:00
Kever Yang
5ae2fd9724 rockchip: clk: rk3399: update driver for spl
Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Added rockchip tag and fix pmuclk_init() build warning:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-16 16:03:43 -06:00