Commit graph

6 commits

Author SHA1 Message Date
Bin Meng
93f8a31186 x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
2015-07-28 10:36:22 -06:00
Simon Glass
90b16d1491 x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.

Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
aad78d2732 dm: x86: pci: Convert chromebook_link to use driver model for pci
Move chromebook_link over to driver model for PCI.

This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)

This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
31f57c2873 x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:41 -06:00
Simon Glass
72cd085aae x86: ivybridge: Add additional LPC init
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
2b6051541b x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00