Commit graph

39369 commits

Author SHA1 Message Date
Stephen Warren
bbc5b36b25 pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.

On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00
Stephen Warren
c04930762d mmc: tegra: port to standard clock/reset APIs
Tegra186 supports the new standard clock and reset APIs. Older Tegra SoCs
still use custom APIs. Enhance the Tegra MMC driver so that it can operate
with either set of APIs.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00
Stephen Warren
34f1c9fe14 i2c: add Tegra186 BPMP driver
On Tegra186, some I2C controllers are directly controlled by the main CPU,
whereas others are controlled by the BPMP, and can only be accessed by the
main CPU via IPC requests to the BPMP. This driver covers the latter case.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00
Stephen Warren
24cdf1a9be power domain: add Tegra186 driver
In Tegra186, SoC power domains are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00
Stephen Warren
4dd99d140c reset: add Tegra186 reset driver
In Tegra186, on-SoC reset signals are manipulated using IPC requests to
the BPMP (Boot and Power Management Processor). This change implements a
driver that does that. It is unconditionally selected by CONFIG_TEGRA186
since virtually any Tegra186 build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00
Stephen Warren
d9fd7008f4 clock: add Tegra186 clock driver
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
(Boot and Power Management Processor). This change implements a driver
that does that. A tegra/ sub-directory is created to follow the existing
pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually
any Tegra186 build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00
Stephen Warren
73dd5c4cfe misc: add Tegra BPMP driver
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work, and
controls related features such as clocks, resets, power domains, PMIC I2C
bus, etc. This driver provides the core low-level communication path by
which feature-specific drivers (such as clock) can make requests to the
BPMP. This driver is similar to an MFD driver in the Linux kernel. It is
unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186
build of U-Boot will need the feature.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:12 -07:00
Tom Rini
f4b0df1823 Merge git://git.denx.de/u-boot-dm 2016-08-12 16:00:50 -04:00
Stephen Warren
b647f55420 misc: add "call" uclass op
The call op requests that the callee pass a message to the underlying HW
or device, wait for a response, and then pass back the response error code
and message to the callee. It is useful for drivers that represent some
kind of messaging or IPC channel to a remote device.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-12 11:01:22 -06:00
John Keeping
aa26776a2d power: pmic: act8846: add missing newline to debug statements
Signed-off-by: John Keeping <john@metanate.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:23:20 -06:00
John Keeping
65f89be2ef power: regulator: act8846: fix reading values
The voltage and control registers need to be looked up from the value in
driver_data.  Adjust the get_value and get_enable functions to match the
corresponding set_* functions.

Signed-off-by: John Keeping <john@metanate.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:23:12 -06:00
Stephen Warren
6e06acb732 fdt: allow fdtdec_get_addr_size_*() to translate addresses
Some code may want to read reg values from DT, but from nodes that aren't
associated with DM devices, so using dev_get_addr_index() isn't
appropriate. In this case, fdtdec_get_addr_size_*() are the functions to
use. However, "translation" (via the chain of ranges properties in parent
nodes) may still be desirable. Add a function parameter to request that,
and implement it. Update all call sites to default to the original
behaviour.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:20:27 -06:00
Stephen Warren
11e44fc6bd fdt_support: fdt_translate_address() blob const correctness
The next patch will call fdt_translate_address() from somewhere with a
"const void *blob" rather than a "void *blob", so fdt_translate_address()
must accept a const pointer too. Constify the minimum number of function
parameters to achieve this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:20:27 -06:00
Masahiro Yamada
ab65006b08 kconfig: use bool instead of boolean for type definition attributes
Linux stopped the use of keyword 'boolean' in Kconfig.

Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-12 09:23:49 -04:00
Mugunthan V N
568d492a07 defconfig: am43xx_evm: enable eth driver model
Enable eth driver model for am43xx_evm as cpsw supports
driver model.

This was already added with the commit bc705ea1cf but with
commit 4c4e3b3775 to add fit support CONFIG_DM_ETH was missed.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-12 09:23:48 -04:00
Lokesh Vutla
1f01962e0f drivers: net: cpsw: always flush cache of size aligned to PKTALIGN
cpsw tries to flush dcache which is not in the range of PKTALIGN.
Because of this the following warning comes while flushing:

CACHE: Misaligned operation at range [dffecec0, dffed016]

Fix it by flushing cache of size aligned to PKTALIGN.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-08-12 09:23:47 -04:00
Mugunthan V N
358133239b configs: dra7xx_evm: enable eth driver model
Enable eth driver model for dra7xx_evm as cpsw supports
driver model.

This was already added with the commit 641b936fa5 but with
commit bd7245849f to add fit support CONFIG_DM_ETH was missed.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2016-08-12 09:23:47 -04:00
Vignesh R
8f521bfc92 ARM: dra7xx_evm: Enable regulator DM support
Enable DM based regulator framework and also fixed regulator support as
some IPs like mmc use regulators for there functioning.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-12 09:22:19 -04:00
Vignesh R
257bdb3f66 ARM: dts: dra7xx-evm: add evm_3v3_sd regulator
Add a node for evm_3v3_sd using onboard PCF GPIO expander which feeds
on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-12 09:22:18 -04:00
Andreas Dannenberg
eba3fbd6a1 common: image: Add support for post-processing of images
This commit allows injecting a board/platform/device-specific post-
processing function into the FIT image data loading process, which can
include modifying the size and altering the starting source address of
an image data artifact. This might be desired to do things like strip
headers or footers attached to the images before they were packaged into
the FIT, or to perform operations such as decryption or authentication.
Introduce new configuration option CONFIG_FIT_IMAGE_POST_PROCESS to
allow controlling this feature. If enabled, a platform-specific post-
process function must be provided.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:22:18 -04:00
Max Filippov
b25732c22b drivers/sysreset: group sysreset drivers
Create drivers/sysreset and move sysreset-uclass and all sysreset
drivers there.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:22:17 -04:00
Stefan Agner
da91cfed54 ARM: non-sec: flush code cacheline aligned
Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-08-12 09:22:15 -04:00
Simon Glass
2651a052d8 i2c: Drop redundant platform data setting in drivers
The i2c uclass has a default setting for per_child_platdata_auto_alloc_size
so drivers do not need to set it. Remove this from drivers to avoid
confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-12 06:41:41 +02:00
Tom Rini
28cd88baa3 Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-08-11 10:45:53 -04:00
Tom Rini
2f1eb66e28 Merge branch 'master' of git://git.denx.de/u-boot-usb 2016-08-11 07:22:55 -04:00
Masahiro Yamada
e8a9293295 ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCs
Currently, only the CPU_ON function is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:58:06 +09:00
Masahiro Yamada
ee9bc77f3a ARM: uniphier: add uniphier_cache_set_active_ways()
This outer cache allows to control active ways independently for
each CPU, so this function will be useful to set up active ways
for a specific CPU.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:45 +09:00
Masahiro Yamada
5941638027 ARM: uniphier: add uniphier_cache_inv_way() to support way invalidation
This invalidates entries in specified ways of the outer cache.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:45 +09:00
Masahiro Yamada
8fca073271 ARM: uniphier: fix CONFIG_SYS_CACHELINE_SIZE when outer cache is on
The UniPhier outer cache (L2 cache on ARMv7 SoCs) has 128 byte line
length and its tags are also managed per 128 byte line.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:44 +09:00
Masahiro Yamada
7382d17826 ARM: uniphier: move (and rename) CONFIG_UNIPHIER_L2CACHE_ON to Kconfig
Move this option to Kconfig, renaming it into CONFIG_CACHE_UNIPHIER.
The new option name makes sense enough, and the same as Linux has.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:38 +09:00
Masahiro Yamada
95646e1d75 ARM: uniphier: move outer cache register macros to .c file
Now, all of these macros are only used in cache-uniphier.c, so
there is no need to export them in a header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:32 +09:00
Masahiro Yamada
c21fadfe17 ARM: uniphier: reuse uniphier_cache_disable() for lowlevel_init
The DRAM is available at this point, so setup the temporary stack
and call the C function to reduce the code duplication a bit.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:31 +09:00
Masahiro Yamada
6f579db754 ARM: uniphier: export uniphier_cache_enable/disable functions
The System Cache (outer cache) is used not only as L2 cache,
but also as locked SRAM.  The functions for turning on/off it
is necessary whether the L2 cache is enabled or not.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:25 +09:00
Masahiro Yamada
bcc51c1512 ARM: uniphier: move lowlevel debug init code after page table switch
As the sLD3 Boot ROM has a complex page table, it is difficult to
set up the debug UART with enabling it.  It will be much easier to
initialize the UART port after switching over to the straight-mapped
page table.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:20 +09:00
Masahiro Yamada
82d075e79f ARM: uniphier: fix ROM boot mode for PH1-sLD3
Commit 4b50369fb5 ("ARM: uniphier: create early page table at
run-time") broke the ROM boot mode for PH1-sLD3 SoC, because the
run-time page table creation requires the outer cache register
access but the page table in the sLD3 Boot ROM does not straight-map
virtual/physical addresses.

The idea here is to check the current page table to determine if
it is a straight map table.  If not, adjust the outer cache register
base.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:14 +09:00
Masahiro Yamada
0efbbc5c61 ARM: uniphier: refactor L2 zero-touching code in lowlevel_init
Here, the ldr pseudo-instruction falls into the ldr + data set.
The register access by [r1, #offset] produces shorter code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:13 +09:00
Masahiro Yamada
e731a5385d ARM: uniphier: do not compile v7_outer_cache_disable if L2 is disabled
If CONFIG_UNIPHIER_L2CACHE_ON is undefined, the L2 cache is never
enabled, so there is no need for v7_outer_cache_disable().  The weak
stub avoids the compile error anyway.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:12 +09:00
Masahiro Yamada
95a1feca2e ARM: uniphier: support prefetch and touch operations for outer cache
The UniPhier outer cache (L2 cache on ARMv7 SoCs) can be used as
SRAM by locking ways.

These functions will be used to transfer the trampoline code for SMP
into the locked SRAM.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:11 +09:00
Masahiro Yamada
3ffc747574 ARM: uniphier: refactor outer cache code
Unify the range/all operation routines into the common function,
uniphier_cache_maint_common(), and sync code with Linux a bit more.

This reduces the code duplication.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-11 17:49:10 +09:00
Tom Rini
2e406dbdf5 Merge git://www.denx.de/git/u-boot-ppc4xx 2016-08-09 07:16:01 -04:00
Alban Bedel
76b2fad775 eth: asix88179: Add support for the driver model
Adjust this driver to support driver model for Ethernet.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
2016-08-09 12:52:05 +02:00
Alban Bedel
620452e7ae eth: asix88179: Prepare supporting the driver model
Change the prototype of a few functions to allow resuing the code for
the driver model.

Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
2016-08-09 12:52:05 +02:00
Dirk Eibach
54a0eb7a18 ppc4xx: Fix platform support
Commit "ecc3066 Fix board init code to respect the C runtime environment"
broke platform support for ppc4xx.
start.S prepares a stackframe that is later rendered unusable by appending
the reserved space for global data.
Instead the reserved space has to be put first. Then the stackframe can
be pushed.

I can only test the 405EP OCM case. At least all other ppc4xx boards still
build.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-08-09 09:25:36 +02:00
Vignesh R
95def3cf5d i2c: i2c-uclass-compat: avoid any BSS usage
As I2C can be used before DRAM initialization for reading EEPROM,
avoid using static variables stored in BSS, since BSS is in DRAM, which
may not have been initialised yet. Explicitly mark "static global"
variables as belonging to the .data section.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Heiko Schocher<hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-08 13:33:00 -04:00
Alexander Graf
0812d1a094 efi_loader: disk: Sanitize exposed devices
When a target device is 0 bytes long, there's no point in exposing it to
the user. Let's just skip them.

Also, when an offset is passed into the efi disk creation, we should
remove this offset from the total number of sectors we can handle.

This patch fixes both things.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-08-08 13:33:00 -04:00
Alexander Graf
f9d334bdfc efi_loader: disk: Fix CONFIG_BLK breakage
When using CONFIG_BLK, there were 2 issues:

  1) The name we generate the device with has to match the
     name we set in efi_set_bootdev()

  2) The device we pass into our block functions was wrong,
     we should not rediscover it but just use the already known
     pointer.

This patch fixes both issues.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-08-08 13:32:59 -04:00
Simon Glass
45313e83b8 tiny-printf: Adjust to avoid using data section
We can pass all the variables down to the functions that need them, and
then everything is on the stack. This is safer than using the data section.

At least on firefly-rk3288, the code size is the same and the data size is
12 bytes smaller:

before:
  18865	   2636	     40	  21541	   5425	b/firefly-rk3288/spl/u-boot-spl
after:
  18865	   2624	     40	  21529	   5419	b/firefly-rk3288/spl/u-boot-spl

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2016-08-08 13:32:59 -04:00
Mugunthan V N
43caa9a879 configs: k2l_evm: add random eth address support
There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-08 13:32:58 -04:00
Mugunthan V N
868a3a6bad configs: k2e_evm: add random eth address support
There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-08 13:32:58 -04:00
Mugunthan V N
02c1e2ff87 configs: k2hk_evm: add random eth address support
There is only one ethernet mac address in e-fuse, but there are
multiple slaves in keystone net, so enable random mac address
support.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-08-08 13:32:57 -04:00