Commit graph

1128 commits

Author SHA1 Message Date
Fabio Estevam
a668a164ff spi: sf_ops: Check the return value from spi_flash_cmd_read_status()
We should check the return value from spi_flash_cmd_read_status() and
propagate it in the case of error.

This fixes a defect caught by Coverity.

Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-18 00:55:29 +05:30
Fabio Estevam
5168721e58 sf: Add lock ops for SST SPI NOR flash
SST SPI NOR flash has the same locking programming bits
as ST Micro - added support for it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
[Minor change on commit message]
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-18 00:26:26 +05:30
Jagan Teki
7693fb3756 sf: Remove eeprom_m95xxx test driver
The relevent boards which used this driver got zapped
in previous release and the driver is never used in the
code and also it doesn't use/do any spi-flash operations.

Commit details for relevent removed boards:
"ARM: at91: remove non-generic boards"
(sha1: f6b42c1403)

Cc: Tom Rini <trini@konsulko.com>
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-11-18 00:01:07 +05:30
Bin Meng
439fcb9b4f sf: Fix NULL pointer exception for flashes without lock methods
commit c3c016c "sf: Add SPI NOR protection mechanism" introduced
flash_lock()/flash_unlock()/flash_is_locked() methods for SPI flash,
but not every flash driver supplies these. We should test these
methods against NULL before actually calling them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-13 09:47:22 -05:00
Maxime Ripard
10b6971215 mtd: uboot: Add meaningful error message
The current error message in get_part if CONFIG_MTDPARTS is disabled is
"offset is not a number" which is confusing and doesn't help at all.

Change that for something that might give a hint on what's going on.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-12 13:17:28 -05:00
Thomas Chou
38a0f36e83 mtd: add altera quadspi driver
Add Altera Generic Quad SPI Controller support. The controller
converts SPI NOR flash to parallel flash interface. So it is
not like other SPI flash, but rather like CFI flash.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-12 08:26:58 +08:00
Thomas Chou
f105691043 cfi_flash: convert to driver model
Convert cfi flash to driver model.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-12 08:26:58 +08:00
Thomas Chou
d85879938d dm: implement a MTD uclass
Implement a Memory Technology Device (MTD) uclass. It should
include most flash drivers in the future. Though no uclass ops
are defined yet, the MTD ops could be used.

The NAND flash driver is based on MTD. The CFI flash and SPI
flash support MTD, too. It should make sense to convert them
to MTD uclass.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
2015-11-12 08:26:58 +08:00
Fabio Estevam
c3c016cf75 sf: Add SPI NOR protection mechanism
Many SPI flashes have protection bits (BP2, BP1 and BP0) in the
status register that can protect selected regions of the SPI NOR.

Take these bits into account when performing erase operations,
making sure that the protected areas are skipped.

Tested on a mx6qsabresd:

=> sf probe
SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB
=> sf protect lock  0x3f0000 0x10000
=> sf erase 0x3f0000 0x10000
offset 0x3f0000 is protected and cannot be erased
SF: 65536 bytes @ 0x3f0000 Erased: ERROR
=> sf protect unlock  0x3f0000 0x10000
=> sf erase 0x3f0000 0x10000
SF: 65536 bytes @ 0x3f0000 Erased: OK

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
[re-worked to fit the lock common to dm and non-dm]
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 16:47:06 -05:00
Fabio Estevam
41b358d7a7 sf: Add SPI protection mechanism from the kernel
Add the SPI NOR protection mechanism from the kernel.

This code is based on the work from
Brian Norris <computersforpeace@gmail.com>
Here is the commit details:
"mtd: spi-nor: refactor block protection functions"
(sha1: 62593cf40b23b523b9fc9334ca61ba6c595ebb09)

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-11-05 16:47:05 -05:00
Fabio Estevam
f8fdb81f6c compat: Remove is_power_of_2() definition
Use the is_power_of_2() definition from log2.h to align with the
kernel implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-11-05 16:46:59 -05:00
Tom Rini
446d37c1ac Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-10-28 16:56:43 -04:00
Tom Rini
714eec71bb Merge git://www.denx.de/git/u-boot-cfi-flash 2015-10-27 19:09:15 -04:00
Tom Rini
2431492aef Merge git://git.denx.de/u-boot-dm 2015-10-27 19:08:19 -04:00
Ryan Harkin
622b95274e cfi_flash: use specific width types for cword
This patch changes the cword union to use specific length types that are
architecture indepented.

This patch also renames the members of the cword union to represent
their usage, i.e.:

    c  -> w8
    s  -> w16
    l  -> w32
    ll -> w64

Where "w" stands for "width" in bits.

I discovered this problem when enabling CFI flash on vexpress64.
cword.l was an unsigned long int, but it was intended to be 32 bits wide.
Unfortunately, it's 64-bits wide on a 64-bit system, meaning that a
64-bit system fails when attempting to use 32-bit wide CFI flash parts.

Similar problems also existed with the other cword sizes.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stefan Roese <sr@denx.de>
2015-10-27 11:51:53 +01:00
Heiko Schocher
248f260cbd UBI: Fastmap: Fix PEB array type
The PEB array is an array of __be32, so let's fix the
scan_pool() prototype accordingly.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-10-26 09:22:50 +01:00
Heiko Schocher
0195a7bb36 ubi,ubifs: sync with linux v4.2
sync with linux v4.2

commit 64291f7db5bd8150a74ad2036f1037e6a0428df2
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date:   Sun Aug 30 11:34:09 2015 -0700

    Linux 4.2

This update is needed, as it turned out, that fastmap
was in experimental/broken state in kernel v3.15, which
was the last base for U-Boot.

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
2015-10-26 09:22:36 +01:00
Jagan Teki
baaaa7539c sf: Add FSR support to spi_flash_cmd_wait_ready
This patch adds flag status register reading support to
spi_flash_cmd_wait_ready.

Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Hou Zhiqiang <B48286@freescale.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
4efad20a17 sf: Update status reg check in spi_flash_cmd_wait_ready
Current flash wait_ready logic is not modular to add new
register status check, hence updated the status check for
adding few more register checks in future.

Below are the sf speed runs with 'sf update' on whole flash, 16MiB.

=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 59.564s, speed 289262 B/s

=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 62.549s, speed 275036 B/s

=> sf update 0x100 0x0 0x1000000
device 0 whole chip
16777216 bytes written, 0 bytes skipped in 61.276s, speed 284359 B/s

Cc: Simon Glass <sjg@chromium.org>
Cc: Marek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
1fabefddfc sf: Make flash->flags use for generic usage
Use the flash->flags for generic usage, not only for dm-spi-flash,
this will be used for future flag additions.

[Correct the spi flash flags detect logic]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
70ccf59406 sf: Optimize BAR write code
Optimized spi-flash bar writing code and also removed
unnecessary bank_sel in read_ops.

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
234a9e1c60 sf: Add spi_flash_read_bar
Add spi_flash_read_bar function for reading bar and
discovering bar commands at probe time.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
3c75ade2b3 sf: Return bank_sel, if flash->bank_curr == bank_sel
If computed bank_sel is same as flash->bank_curr which is
computed at probe time, then return the bank_sel instead of zero.

Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
720e5e54eb sf: params: Add IS25LP128 part support
Added support for IS25LP128 flash part.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:03 +05:30
Jagan Teki
65a75b6f7a sf: params: Add IS25LP064 part support
Added support for IS25LP064 flash part.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:02 +05:30
Jagan Teki
24ea6ac892 sf: params: Add IS25LP032 part support
Added support for IS25LP032 flash part.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
2015-10-25 20:17:02 +05:30
Simon Glass
bcbe3d1579 dm: Rename dev_get_parentdata() to dev_get_parent_priv()
The current name is inconsistent with other driver model data access
functions. Rename it and fix up all users.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2015-10-23 09:42:28 -06:00
Tom Rini
cb4c833b74 Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-10-15 08:43:38 -04:00
Stefan Agner
e24bb2b732 mtd: nand: vf610_nfc: resync with upstream Linux version
This resyncs the driver changes with the Linux version of the
driver. The driver received some feedback in the LKML and got
recently acceppted, the latest version can be found here:
https://lkml.org/lkml/2015/9/2/678

Notable changes are:
- On ECC error, reread OOB and count bit flips in OOB too.
  If flipped bits are below threshold, also return an empty
  OOB buffer.
- Return the amount of bit flips in vf610_nfc_read_page.
- Use endianness aware vf610_nfc_read to read ECC status.
- Do not enable IDLE IRQ (since we do not operate with an
  interrupt service routine).
- Use type safe struct for buffer variants (vf610_nfc_alt_buf).
- Renamed variables in struct vf610_nfc (column and page_sz)
  to reflect better what they really representing.

The U-Boot version currently does not support RAW NAND write
when using the HW ECC engine.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-10-15 11:10:44 +02:00
Ezequiel García
d1d0167663 nand: omap_gpmc: Change correctable bit-flips messages to debug()
Messages on corrected bit-flips are not really useful,
as bit-flips are perfectly normal. Let's avoid cluttering
the console and make them debug.

Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
2015-10-11 17:12:13 -04:00
Yao Yuan
f2b76c6037 mtd: sf: Add support AT26DF081A chip
AT26DF081A is the spi flash type of TWR-MEM(SCH-26248) card.
We can access the flash through DSPI2 on LS1021ATWR board.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-10-11 16:43:06 +05:30
Hans de Goede
31c5614af4 sunxi_nand_spl: Be smarter about where to look for backup u-boot.bin
We know when u-boot is written to its own partition, in this case the
layout always is:

eb 0 spl
eb 1 spl-backup
eb 2 u-boot
eb 3 u-boot-backup

eb: erase-block

So if we cannot load u-boot from its primary offset we know exactly where
to look for it.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-09-29 11:50:07 +02:00
Peng Fan
168617c9b5 mtd: nand: mxs check maximum ecc that platfrom supports
Check maximum ecc strength for each platfrom to avoid the calculated ecc
exceed the limitation.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Han Xu <b45815@freescale.com>
Tested-By: Tim Harvey <tharvey at gateworks.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
2015-09-20 09:59:54 +02:00
Stefan Roese
62c390f8a3 mtd: nand: fsmc: Fixes and cleanup for fsmc_nand_switch_ecc()
This patch addresses some comments raised by Scott in the last versions.
Here the changes in detail:

- Removed __maybe_unused as its not needed
- Added check for strength == 4 and error out for the unsupported
  ECC strength values
- Don't set .caclulate, .correct, and .bytes for NAND_ECC_SOFT_BCH as this
  will be done in nand_scan_tail()
- Set .caclulate back to fsmc_read_hwecc() in the HW case
- Added comment that this function will only be called on SPEAr platforms,
  not supporting the BCH8 HW ECC (FSMC_VER8)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-09-15 15:05:21 -04:00
Heiko Schocher
92a3188d7d bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-09-11 17:15:32 -04:00
Simon Glass
cf92e05c01 Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header
Now that we have a new header file for cache-aligned allocation, we should
move the stack-based allocation macro there also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 17:15:20 -04:00
Simon Glass
6e295186c7 Move malloc_cache_aligned() to its own header
At present malloc.h is included everywhere since it recently was added to
common.h in this commit:

   4519668 mtd/nand/ubi: assortment of alignment fixes

This seems wasteful and unnecessary. We have been trying to trim down
common.h and put separate functions into separate header files and that
change goes in the opposite direction.

Move malloc_cache_aligned() to a new header so that this can be avoided.
The header would perhaps be better named as alignmem.h but it needs to be
included after common.h and people might be confused by this. With the name
memalign.h it fits nicely after malloc() in most cases.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2015-09-11 17:15:16 -04:00
Stefan Roese
1a103c6caa mtd: nand: fsmc: Add BCH4 SW ECC support for SPEAr600
This patch adds support for 4-bit ECC BCH4 for the SPEAr600 SoC. This can
be used by boards equipped with a NAND chip that requires 4-bit ECC strength.
The SPEAr600 HW ECC only supports 1-bit ECC strength.

To enable SW BCH4, you need to specify this in your config header:

#define CONFIG_NAND_ECC_BCH
#define CONFIG_BCH

And use the command "nandecc bch4" to select this ECC scheme upon runtime.

Tested on SPEAr600 x600 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2015-09-11 17:15:13 -04:00
Simon Glass
0abdd9d01a arm: Remove nhk8815 boards and nomadik arch
These boards have not been converted to generic board by the deadline.
Remove them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-11 14:56:04 -04:00
Stefan Roese
cc19722f04 sunxi_nand_spl: Add config parameter for 4KiB page sized NAND devices
This patch adds support for NAND chips with 4KiB page size and 24/1024
ECC strength. Like the Micron MT29F32G08CBACAWP which is used on the
ICnova-A20 SoM.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-09-10 20:20:45 +02:00
Hans de Goede
d90ba790d8 mtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig
Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like
SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends,
to avoid double defining it for SoCs which have not yet moved to Kconfig
for this.

Having this in Kconfig is useful because this is something which may
differ from one board to the other even when using the same SoC.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-08-31 08:43:42 +02:00
Boris Brezillon
ddd37fe865 sunxi_nand_spl: clear status flags in SPL implementation
Some status flags remain set until you explicetly clear the bit
in the status register.
Fix the SPL implementation to avoid false positive.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
[hdegoede@redhat.com: Port from v2015.07 to v2015.10]
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-31 08:43:42 +02:00
Hans de Goede
6a08d65acc sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_END
We only ever use syndrome mode for the partitions which contain the SPL,
as that is required for the BROM to be able to read the SPL.

Instead of using some arbritray limit for deciding whether or not to
use syndrome, be smart and check if u-boot-dtb.bin is directly behind
the SPL, if it is not then it is on its own partition and we should not
use syndrome.

Note the reason why we only use syndrome mode for the SPL is because it
comeswith weaker randomization, introducing a risk for more bit errors,
so we want to avoid it when possible.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
e526861687 sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXI
We eventually want to add full nand support, since it makes no sense
to build SPL with nand support and u-boot without, or the other way
around, a single option will suffice.

Renaming the Kconfig option now makes things easier when we add full
nand support in the future.

The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an
"ifdef CONFIG_SPL_BUILD" block in the Makefile.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
24a06c964f sunxi_nand_spl: Add support for backup boot partitions
The BROM does not care / use bad page markings, instead it deals with
any bad pages in the first erase-block by simply trying to load "boot0"
from the next erase-block.

This commit implements the same strategy for the sunxi spl nand code,
allowing it to boot from the backup boot partition when the main boot
partition is bad (tested by erasing the main boot partition).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
2b8a01a99d sunxi_nand_spl: Auto detect nand configuration parameters
Auto detect the nand configuration parameters, like the BROM does.

This allows us to get rid of various Kconfig settings, and is
necessary to support generic boards like the mk802 which have seen
many production runs with different nands.

The full blown u-boot/kernel nand driver uses the nand id to determine
this info, for the SPL we do as the BROM does and simply try a few
standard configs.

Note the table only contains configs which are known to actually be used,
rather then all the configs the BROM tries. This means that it may need
to be updated in the future as we add support for nand on more boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
f5916d1856 sunxi_nand_spl: Parametrize lowlevel read functions
Parametrize the lowlevel nand_read_page function, instead of directly
using the CONFIG_foo settings for page-size, etc. there and add a few
wrappers / helper functions for calling it.

This is a preparation patch for adding auto-detecting of the nand
parameters like the BROM does.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
0a247554c2 sunxi_nand_spl: Properly config page-size in the nand ctl register
Properly config page-size in the nand ctl register, it seems that things
work fine without doing this, but still lets play it safe and properly
set the page-size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
022a99d8b2 sunxi_nand_spl: Add support for sun4i and sun5i SoCs
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.

Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
008ac1dfe0 sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _off
Sync the code for figuring out the ecc_mode and ecc_offset with the linux
kernel v4.1. Keeping this in sync seems like a good idea in general, and
it fixes / adds support for ecc strengths of 56, 60 and 64 bits.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
2a43973f64 sunxi_nand_spl: Add proper cache flusing
We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.

Things are working without this by mostly luck, but lets not rely on that.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
5d65c67bf1 sunxi_nand_spl: Turn off clocks when we're done with the nand
Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.

Without this the kernel will not boot properly when it is built with
dma-controller support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
f62bfa56da sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessary
Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
9da5fca55c sunxi_nand_spl: Do not bother writing the spare-area reg in syndrome mode
In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE"
not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE.

So the current code only serves to confuse the user -> remove it.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
630cf2e762 sunxi_nand_spl: We only need to reset the nand chip once
There is no need to reset the nand chip for every ecc-block read.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
10d069b797 sunxi_nand_spl: Drop unnecessary temp buf
nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and have plenty of space for "overshooting" up to
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks.

This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in
SPL size, which is a lot on the total 24k we have.

Note this changes the dma destination from SRAM to DRAM, so this patch
updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Masahiro Yamada
2bc1f2b592 mtd: denali_spl: do not allocate page_buffer in .bss section
Since commit 2580a2a7e7 ("mtd: nand: Increase max sizes of OOB and
Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build
with the following error message:
  arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big

They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer
as static data:

    static uint8_t page_buffer[NAND_MAX_PAGESIZE];

This buffer required 8KB in .bss section before that commit and now
it has been increased to 16KB.  Given limited code/memory size for SPL,
it is not a good idea to allocate a page buffer statically.  In the
first place, the load address 'dst' can be used as a page buffer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-08-30 22:18:00 +09:00
Marcel Ziswiler
4519668b29 mtd/nand/ubi: assortment of alignment fixes
Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:

ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
[trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:17 -04:00
Peng Fan
ecfb8768b1 mtd: nand: mxs invalidate dcache before DMA read
Follow linux dma flow:
Before DMA read, be sure to invalidate the cache over the address
range of DMA buffer to prevent cache coherency problems.
After DMA read, invalidate dcache again.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2015-08-25 22:53:59 -05:00
Peng Fan
63b29d8082 mtd: nand: mxs support oobsize bigger than 512
If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.

The following graph is modified from kernel gpmi-nand.c driver with
each data block 512 bytes. We can see that Block Mark conflicts with
ecc area from bch view. We can enlarge the ecc chunk size to avoid
this problem to those oobsize which is larger than 512.

   |                          P                                        |
   |<----------------------------------------------------------------->|
   |                                                                   |
   |                                                (Block Mark)       |
   |                      P'                             |           | |   |
   |<--------------------------------------------------->|     D     | | O'|
   |                                                     |<--------->| |<->|
   V                                                     V           V V   V
   +---+--------------+-+--------------+-+--------------+-+----------+-+---+
   | M |   data       |E|   data       |E|   data       |E|   data   |E|   |
   +---+--------------+-+--------------+-+--------------+-+----------+-+---+
                                                        ^                  ^
                                                        |         O        |
                                                        |<---------------->|

       P : the page size for BCH module.
       E : The ECC strength.
       G : the length of Galois Field.
       N : The chunk count of per page.
       M : the metasize of per page.
       C : the ecc chunk size, aka the "data" above.
       P': the nand chip's page size.
       O : the nand chip's oob size.
       O': the free oob.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com>
2015-08-25 22:53:58 -05:00
Stefan Roese
873960c89e mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driver
Cloned from the Linux driver v4.2.0-rc2. Plus some patches from
Antoine Tenart enabling controller initialization and ONFI timing
support:

http://lists.infradead.org/pipermail/linux-mtd/2015-July/060197.html

Please note that this driver needs the Linux NAND subsystem sync to v4.1
from Scott to be applied:

https://www.mail-archive.com/u-boot@lists.denx.de/msg175762.html

Otherwise it will not compile.

Tested on the Marvell Armada XP DB-MV784MP-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: Ezeguil Garcia <ezequiel.garcia@free-electrons.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:58 -05:00
Scott Wood
d3963721d9 nand: Sync with Linux v4.1
Update the NAND code to match Linux v4.1.  The previous sync was
from Linux v3.15 in commit 4e67c57125.

CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now
has its own timeout.  Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented
and not selected by any board.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:57 -05:00
Ezequiel Garcia
86a720aafc mtd: Introduce mtd_block_isreserved()
In addition to mtd_block_isbad(), which checks if a block is bad or
reserved, it's needed to check if a block is reserved only (but not
bad). This commit adds an MTD interface for it, in a similar fashion to
mtd_block_isbad().

While here, fix mtd_block_isbad() so the out-of-bounds checking is done
before the callback check.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[scottwood: Cherry-picked from Linux 8471bb73ba10ed67]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:57 -05:00
Scott Wood
273310644f nand: Remove __UBOOT__ ifdefs
I didn't approve the patch that added them.  Get them out of the way
before doing a sync.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-08-25 22:53:57 -05:00
Masahiro Yamada
0f9258228e of: clean up OF_CONTROL ifdef conditionals
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL.  We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:

 #ifdef CONFIG_OF_CONTROL
 # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
 #  define OF_CONTROL 0
 # else
 #  define OF_CONTROL 1
 # endif
 #else
 # define OF_CONTROL 0
 #endif

Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute.  It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.

Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-18 13:46:05 -04:00
Sylvain Lemieux
30cb3bf4a9 nand: lpc32xx: add ECC layout for small page NAND
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)

This layout is matching the lpc32xx NAND SLC Linux Kernel driver.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-08-18 13:45:56 -04:00
Sylvain Lemieux
5f63bf3ec8 nand: lpc32xx: add hardware ECC support
Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250 header file missing SLC NAND registers definition

The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
2015-08-18 13:45:56 -04:00
Tom Rini
146bad9619 sf: ops: Add spi_flash_copy_mmap function
When doing a memory mapped copy we may have DMA available and thus need
to have this copy abstracted so that the driver can do it, rather than a
simple memcpy.

Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17 23:29:14 +05:30
Marek Vasut
0a02655481 sf: Make 4K sector support configurable
Make the support for 4K subpage I/O on a SPI NOR flash configurable.
A board which requires the SPI NOR to be accessed in larger 32KiB
or 64KiB pages can disable the 4K subpage support, but by default,
the support for 4K subpage I/O is enabled. The functionality of this
option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux.

This is extremely useful in case one uses UBI on a SPI NOR flash.
UBI needs at least 15k EBs and can not work on a flash which uses
4k ones, so disabling the support for 4k subpages lets UBI work on
such flash.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-17 15:59:48 +05:30
Marcel Ziswiler
6eeedc196d tegra: nand: disable subpage writes
Disable subpage writes as we do not provide ecc->hwctl.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:03 -07:00
Marcel Ziswiler
adf4800d85 mtd/nand/tegra: alignment workaround
Integrate cache alignment bounce buffer to workaround issues as follows:

Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)...
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
Done
Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ]

Starting kernel ...

undefined instruction
pc : [<005ff03c>]          lr : [<0000800c>]
sp : 0144b6e8  ip : 01000188     fp : 0144a6c8
r10: 00000000  r9 : 411fc090     r8 : 00000100
r7 : 00000cfb  r6 : 0144a6d0     r5 : 00000000  r4 : 00008000
r3 : 0000000c  r2 : 00000100     r1 : 00000cfb  r0 : 00000000
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:02 -07:00
Marcel Ziswiler
1bc66a57c0 tegra: nand: fix read_byte required for proper onfi detection
Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command required for proper ONFI detection.

This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late
(not mainline yet but getting there soon I hope).

I vaguely remember that those commands are special on 16-bit bus NAND
(e.g. always return 8-bit data regardless) and later Linux MTD fixed/
changed the way this is handled which in turn broke once U-Boot pulled
that in. Basically instead of doing PIO read regular DMA block read is
now used which this patch actually fixes.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:02 -07:00
Vladimir Zapolskiy
dcfd37e5ef nand: lpc32xx: add SLC NAND controller support
The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
2015-08-12 20:47:33 -04:00
Vladimir Zapolskiy
8d1809a966 spl: nand: simple: replace readb() with chip specific read_buf()
Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-08-12 20:47:33 -04:00
Heiko Schocher
c10ac540ea nand, atmel: remove udelay in spl_nand_erase_one()
remove unneeded udelay() in this function, as we use
the dev_ready pin.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
2015-08-12 20:47:27 -04:00
Piotr Zierhoffer
960caeba8f sunxi: nand: Add board configuration options
When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.

This commit also introduces the configurable options in Kconfig.

Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-08 16:26:19 +02:00
Piotr Zierhoffer
aeb4b0d3b3 sunxi: nand: Add basic sunxi NAND driver for SPL with DMA support
This driver adds NAND support to SPL.
It was tested on Allwinner A20.

Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-08 16:26:19 +02:00
Nikita Kiryanov
d5af92315b sf: kconfig: add kconfig options for spi flashes
Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig.

Cc: Jagan Teki <jteki@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2015-08-02 10:51:39 +02:00
Masahiro Yamada
f18d11163e mtd: fix false positive "Offset exceeds device limit" error
Since commit 09c3280754 (mtd, nand: Move common functions from
cmd_nand.c to common place), NAND commands would not work at all
on large devices.

    => nand read 80000000 10000 10000

    NAND read: Offset exceeds device limit
    => nand erase 100000 100000

    NAND erase: Offset exceeds device limit

The type of the "size" of "struct mtd_info" is uint64_t, while
mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type.
The chipsize is wrapped around if the argument is given with 2GB
or larger.

Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-07-10 09:38:50 -04:00
Jagan Teki
84d31b3b8f sf: Kconfig: Add SPI_FLASH_BAR entry
Added SPI_FLASH_BAR entry on Kconfig with help description

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:39:06 +05:30
Jagan Teki
cd9accdcd9 sf: Kconfig: Add SPI_FLASH_DATAFLASH entry
Added SPI_FLASH_DATAFLASH entry on Kconfig with help description.

data flash driver comes with good decription, hence moved the
same on to kconfig help decription.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Haikun Wang <haikun.wang@freescale.com>
2015-07-01 21:22:19 +05:30
Jagan Teki
7678dd93ec sf: Kconfig: Add SPI_FLASH_MTD entry
Added SPI_FLASH_MTD entry on Kconfig with help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
2015-07-01 21:15:04 +05:30
Jagan Teki
2ce7e2b6fc sf: Kconfig: Update SPI_FLASH entry
Updated SPI_FLASH entry on Kconfig with depends on
and along with config help description.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:04 +05:30
Jagan Teki
810fd69672 sf: Add Kconfig menu entry
Added Kconfig menu ... endmenu enties for spi flash suppor

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:04 +05:30
Jagan Teki
6812484a40 sf: dataflash: Rename to CONFIG_SPI_FLASH_DATAFLASH
Rename CONFIG_SF_DATAFLASH into CONFIG_SPI_FLASH_DATAFLASH
as it follows the naming convention same as remaining configs.

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:04 +05:30
Jagan Teki
5d69df3541 spi/sf: Minor cleanups
- Adjust tab spaces
- Add comments

Signed-off-by: Jagan Teki <jteki@openedev.com>
2015-07-01 21:15:03 +05:30
Haikun Wang
9c5a70dbe8 sf: update sst25wf040b flash params
sst25wf040b doesn't support Auto Address Increment Programming command.
Remove SST_WR flag.

Signed-off-by: Haikun Wang <B53464@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-06-30 01:20:37 +05:30
Heiko Schocher
09c3280754 mtd, nand: Move common functions from cmd_nand.c to common place
Move common functions from cmd_nand.c (for calculating offset
and size from cmdline paramter) to common place, so they could
used from other commands which use mtd partitions.

For onenand the arg_off_size() is left in common/cmd_onenand.c.
It should use now the common arg_off() function, but as I could
not test onenand I let it there ...

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-06-30 00:40:11 +05:30
Daniel Schwierzeck
9fe6d8716e mtd, spi: Add MTD layer driver
Add MTD layer driver for spi, original patch from:
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=bb246819cdc90493dd7089eaa51b9e639765cced

Changes from Heiko Schocher against this patch:
- Remove compile error if not defining CONFIG_SPI_FLASH_MTD:

  LD      drivers/mtd/spi/built-in.o
drivers/mtd/spi/sf_probe.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
drivers/mtd/spi/sf_ops.o: In function `spi_flash_mtd_unregister':
/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: multiple definition of `spi_flash_mtd_unregister'
drivers/mtd/spi/sf_params.o:/home/hs/abb/imx6/u-boot/drivers/mtd/spi/sf_internal.h:168: first defined here
make[1]: *** [drivers/mtd/spi/built-in.o] Fehler 1
make: *** [drivers/mtd/spi] Fehler 2

- Add a README entry.
- Add correct writebufsize, to fit with Linux v3.14
  MTD, UBI/UBIFS sync.

Note (From Jagan): For testing raw mtd parition erase/read/write operations
using cmd_sf, sf_mtd should be required to register the spi flash device to
MTD layer but the sf_mtd_info ops were not required until and unless if we
use any flash filesystem layer say for example UBI. Due to this the foot-print
got increased ~290bytes in non-UBI case here that should be acceptible.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Jagannadh Teki <jteki@openedev.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
2015-06-30 00:40:11 +05:30
Haikun Wang
79b4c08fc4 dm: sf: Add Atmel DataFlash spi flash driver
Atmel DataFlash chips have commands different from common spi
flash commands.
Atmel DataFlash also have special page-size.
This driver add support for accessing Atmel DataFlash.
It is based on the Driver Model.
Example:
=> sf probe 1:0
SPI DataFlash: Detected AT45DB021B with page size 264 Bytes, erase size 264 Bytes, total 264 KiB, revision d
=> sf erase 0 42000
SF: 270336 bytes @ 0x0 Erased: OK
=> mw.l 82000000 45444342 20000
=> sf write 82000000 0 42000
SF: 270336 bytes @ 0x0 Written: OK
=> sf read 83000000 0 42000
SF: 270336 bytes @ 0x0 Read: OK
=> cmp.b 82000000 83000000 42000
Total of 270336 byte(s) were the same

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Tested-by: Haikun Wang <haikun.wang@freescale.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Chakra Divi <cdivi@openedev.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-06-30 00:40:10 +05:30
Ian Campbell
da9971d1b3 Revert "sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory"
This reverts commit f76eba38b3.

This patch did not have a full and proper copyright/S-o-b chain.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>

Conflicts:
	include/configs/sun6i.h
	include/configs/sun8i.h
2015-06-28 11:46:31 -04:00
Joe Hershberger
22e04faaab mtd: spi: Add the SPI_FLASH config to Kconfig
This config needs to be available in the Kconfig to allow it to be
removed from arch defaults.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-06-25 17:04:43 -04:00
Jeroen Hofstee
cb2fc338f8 mtd: OMAP: Enable GPMC prefetch mode for 16 bit access
commit c316f57 "mtd: OMAP: Enable GPMC prefetch mode" only enabled
prefetch mode for 8 bit nand access, this adds 16 bit as well.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-18 11:23:45 -04:00
Jeroen Hofstee
c07361145f omap_gpmc: move prefetch out of CONFIG_NAND_OMAP_ELM
The prefech mode is a feature of the gpmc, not the ELM. An am3517
does not have an elm, but can do prefeches, so move the code out
of the CONFIG_NAND_OMAP_ELM ifdef.

Cc: Scott Wood <scottwood@freescale.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Daniel Mack <zonque@gmail.com>

Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-06-18 11:23:45 -04:00
Daniel Kochmański
f76eba38b3 sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memory
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.

Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-05-29 13:46:36 +02:00
Stefan Agner
8fca2d8cb8 mtd: vf610_nfc: enable ONFI detection
This changes enable ONFI detection. The Read ID command now allows
one address byte which is needed for ONFI detection. To read the
ONFI parameter page, the NAND_CMD_PARAM need to be supported. The
CMD code enables one command and one address byte along with reading
data from flash using R/B#, as specified by ONFI.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:27:46 -05:00
Stefan Agner
080a71e8e9 mtd: vf610_nfc: add 32-error correction option for HW ECC
Add option to choose between current 24-error correction and 32-error
correction through Kconfig. 32-error correction allow to use NAND
chips which require up to 8-bit error correction per 512 byte (when
using 2K pages).

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:27:46 -05:00
Stefan Agner
5519194d4f mtd: vf610_nfc: add Freescale NFC controller configs to Kconfig
This commit allows users to enable/disable the Freescale NFC
controller found in systems like Vybrid (VF610), MPC5125, MCF54418
or Kinetis K70 via Kconfig with more detailed help docs.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Stefano Babic <sbabic@denx.de>
[scottwood: updated vf610twr_nand_defconfig]
Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-05-24 14:27:28 -05:00
Stefan Agner
84d656a283 mtd: vf610_nfc: use in-band bad block table
Use in-band bad block table (NAND_BBT_NO_OOB) which allows to
use the full OOB for hardare ECC purposes. Since there is no
ECC correction on the OOB it is also safer to use in-band area
to store the bad block table marker.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:26:55 -05:00
Stefan Agner
5dec286b82 mtd: vf610_nfc: implement OOB only read
Implement read of OOB area only. When using column and sector size
properties, only parts of the page can be read. However, this works
only when hardware ECC is disabled, otherwise the ECC engine would
ruin the data in the buffer. To allow OOB only reads, three points
had to be addressed:
- Set ECC mode per command.
- Handle NAND_CMD_READOOB seperate. Make sure column and sector
  size is correctly set up, while disabling ECC.
- Now, the OOB data end up at the beginning of the buffer. Remove
  the special handling of OOB (spareonly).

Especially bad block scans benefit from this change. On a 512MiB
SLC NAND device, the bad block scan took 1.5s less than before.

Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-05-24 14:26:55 -05:00