Commit graph

54486 commits

Author SHA1 Message Date
Daniel Schwierzeck
8da7495299 mips: xilfpga: fix DTC warnings
This fixes following DTC warning:

arch/mips/dts/nexys4ddr.dtb: Warning (compatible_is_string_list): /ethernet@10e00000/mdio/phy@1:compatible: property is not a string list

As upstream DTS in Linux doesn't have the offending property,
simply remove it to fix the warning.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Daniel Schwierzeck
d2f02586fd mips: ath79: fix DTC warnings
Remove all interrupt nodes that cause warnings regarding a missing
interrupt parent. There are no interrupt controller nodes defined
and the device trees don't match the ones in Linux anymore.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
a4bfa0e969 bmips: enable ar-5315u enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
93bd64bf05 bmips: bcm6318: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
173e3aec81 bmips: enable vr-3032u enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
b07f2dc6a0 bmips: bcm63268: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
ba329fd1f2 bmips: enable dgnd3700v2 enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
4518a24c29 bmips: bcm6362: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
54468f5853 bmips: enable ar-5387un enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
45934ed846 bmips: bcm6328: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
2e498f23ac bmips: enable wap-5813n enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
d9c1f0c23f bmips: bcm6368: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
9622972af4 net: add support for bcm6368-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
9c0c7e8487 bmips: enable nb4-ser enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
15591a9ae1 bmips: enable hg556a enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
4f88720e6a bmips: bcm6358: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
eb4bdc7cc2 bmips: enable ct-5361 enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
9dc07b9493 bmips: bcm6348: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
ec96de3b66 bmips: enable f@st1704 enet support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:01 +01:00
Álvaro Fernández Rojas
d7f5bc1aea bmips: bcm6338: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
55e55fe4a6 net: add support for bcm6348-enet
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
6e0faa22dd bmips: bcm6318: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
83eae02462 bmips: bcm63268: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
b2bf5a2243 bmips: bcm6362: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
85132221e2 bmips: bcm6328: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
0417eb5590 bmips: bcm6368: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
487250e6df bmips: bcm6358: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
c225d6619e bmips: bcm6348: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
9ab403d0dd bmips: bcm6338: add bcm6348-iudma support
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
2018-12-19 15:23:00 +01:00
Álvaro Fernández Rojas
ccfd69883a dma: add bcm6348-iudma support
BCM6348 IUDMA controller is present on multiple BMIPS (BCM63xx) SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-12-19 15:23:00 +01:00
Rick Chen
368ff57805 doc: README.ae350: Sync for ax25-ae350 rename
Rename ax25-ae350 as ae350_rv[32|64] for 32 or 64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 13:26:02 +08:00
Rick Chen
ab3f92dee6 riscv: configs: Rename ax25-ae350 defconfig
Remove cpu name from the defconfig naming.
Because other cpus maybe run on AE350 platform.
So only use platfrom name in defconfig naming
will be better.

Also sync MAINTAINERS:
Rename
a25-ae350_32_defconfig as ae350_rv32_defconfig
ax25-ae350_64_defconfig as ae350_rv64_defconfig

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 13:25:55 +08:00
Anup Patel
9acaf60bfd riscv: qemu: Imply SIFIVE_SERIAL for emulation
This patch enables SiFive UART driver for QEMU RISC-V emulation
by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
Anup Patel
e2842496ac drivers: serial: Add SiFive UART driver
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.

Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2018-12-18 09:56:54 +08:00
Bin Meng
dcad9b8d66 riscv: Remove ae350.dts
This is not used by any board. Remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
3c85099aa3 riscv: bootm: Change to use boot_hart from global data
Avoid reading mhartid CSR directly, instead use the one we saved
in the global data structure before.

With this patch, BBL no longer needs to be hacked to provide the
mhartid CSR emulation for S-mode U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
51ab4570f3 riscv: Save boot hart id to the global data
At present the hart id passed via a0 in the U-Boot entry is saved
to s0 at the beginning but does not preserve later. Save it to the
global data structure so that it can be used later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
7f5d35a547 riscv: Adjust the _exit_trap() position to come before handle_trap()
With this change, we can avoid a forward declaration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
10753ef8fd riscv: Return to previous privilege level after trap handling
At present the trap handler returns to hardcoded M-mode/S-mode.
Change to returning to previous privilege level instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
496262cca6 riscv: Fix context restore before returning from trap handler
sp cannot be loaded before restoring other registers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
4b3f5ed5ac riscv: Move trap handler codes to mtrap.S
Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
485e822346 riscv: Do some basic architecture level cpu initialization
In arch_cpu_init_dm() do some basic architecture level cpu
initialization, like FPU enable, etc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
57fe5c64cb riscv: Add indirect stringification to csr_xxx ops
With current csr_xxx ops, we cannot pass a macro to parameter
'csr', hence we need add another level to allow the parameter
to be a macro itself, aka indirect stringification.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
aef59e5cc4 riscv: Update supports_extension() to use desc from cpu driver
This updates supports_extension() implementation to use the desc
string from the cpu driver whenever possible, which avoids the
reading of misa CSR for S-mode U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
3967156464 riscv: Add exception codes for xcause register
This adds all exception codes in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
ea53f1c742 riscv: Add CSR numbers
The standard RISC-V ISA sets aside a 12-bit encoding space for up
to 4096 CSRs. This adds all known CSR numbers as defined in the
RISC-V Privileged Architecture Version 1.10.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
3c276b2703 riscv: Remove non-DM version of print_cpuinfo()
With DM CPU driver, the non-DM version of print_cpuinfo() is no
longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
39cad5bc0b riscv: Probe cpus during boot
This calls cpu_probe_all() to probe all available cpus.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
92b64fef05 riscv: Enlarge the default SYS_MALLOC_F_LEN
Increase the heap size for the pre-relocation stage, so that CPU
driver can be loaded.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00
Bin Meng
84304d4866 riscv: qemu: Add platform-specific Kconfig options
Add the QEMU RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-18 09:56:27 +08:00