Commit graph

27609 commits

Author SHA1 Message Date
Thierry Reding
7dd8738f08 ARM: tegra: Enable PCIe on TrimSlice
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
65d2465d5d ARM: tegra: Add Tegra20 PCIe device tree node
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
f315828b0d pci: tegra: Add Tegra PCIe driver
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
b02f3e0c2d ARM: tegra: Enable XUSB pad controller on Jetson TK1
Add the PCIe and SATA lane configuration to the Jetson TK1 device tree,
so that the XUSB pad controller can be appropriately configured.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
78e9f1c4f3 ARM: tegra: Add XUSB pad controller on Tegra124
The XUSB pad controller is used for pinmuxing of the XUSB, PCIe and SATA
lanes.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
79c7a90f6c ARM: tegra: Implement XUSB pad controller
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
48510c089b ARM: tegra: Implement powergate support
Implement the powergate API that allows various power partitions to be
power up and down.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
59cb3bf4c6 ARM: tegra: Provide PCIEXCLK reset ID
This reset is required for PCIe and the corresponding ID therefore needs
to be defined. The enumeration value for this was properly defined on
some SoCs but not on others. Similarly, some contained it in the mapping
of peripheral IDs to clock IDs, other didn't. This patch defines it
consistently for all supported SoC generations.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
a723074550 ARM: tegra: Implement tegra_plle_enable()
This function is required by PCIe and SATA. This patch implements it on
Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because
it doesn't support PCIe or SATA.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
6173c45b21 power: Add AMS AS3722 PMIC support
The AS3722 provides a number of DC/DC converters and LDOs as well as 8
GPIOs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
ed710457a5 ARM: Implement non-cached memory support
Implement an API that can be used by drivers to allocate memory from a
pool that is mapped uncached. This is useful if drivers would otherwise
need to do extensive cache maintenance (or explicitly maintaining the
cache isn't safe).

The API is protected using the new CONFIG_SYS_NONCACHED_MEMORY setting.
Boards can set this to the size to be used for the non-cached area. The
area will typically be right below the malloc() area, but architectures
should take care of aligning the beginning and end of the area to honor
any mapping restrictions. Architectures must also ensure that mappings
established for this area do not overlap with the malloc() area (which
should remain cached for improved performance).

While the API is currently only implemented for ARM v7, it should be
generic enough to allow other architectures to implement it as well.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-18 21:18:43 +01:00
Marcel Ziswiler
839e4f7c66 ARM: tegra: colibri_t30: comment style fix
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 12:47:11 -07:00
Tom Rini
7a7ffedabd Merge branch 'master' of git://git.denx.de/u-boot-usb 2014-12-18 12:37:18 -05:00
Masahiro Yamada
d8bec60c1b ARM: UniPhier: enable CONFIG_CMD_DM
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:30 +09:00
Masahiro Yamada
992e874885 ARM: UniPhier: select CONFIG_SPL
Now UniPhier platform is only supported with SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:27 +09:00
Masahiro Yamada
7e421d640b ARM: UniPhier: use DRAM area for init stack of normal image
The normal image is working on DRAM.  It is better to use DRAM also
for init stack than L2 cache.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:25 +09:00
Masahiro Yamada
d4d45ead23 ARM: UniPhier: remove unnecessary ifdef conditional
init_page_table is only set on SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:12 +09:00
Masahiro Yamada
490f55c4a6 ARM: UniPhier: fix property names of aliases nodes of device trees
The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-18 23:34:01 +09:00
Adnan Ali
babe6994ca sf: sf_params: Add S25FL164K flash identifier info
Add the necessary flash entry for the Spansion S25FL164K
flash. Tested on Marvell 88F6218 based design.

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18 18:48:30 +05:30
Adnan Ali
cf156007e0 sf: sf_params: Add S25FL116K flash support
Added S25FL116K flash and tested on Marvell 88F6281 based system.

Signed-off-by: Adnan Ali <adnan.ali@codethink.co.uk>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18 18:45:35 +05:30
Shengzhou Liu
b45a3de086 mtd/spi: Add support for SST25WF040B
Add support for SST25WF040B-40I-SN flash.
Tested on T1024QDS board.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-18 18:19:24 +05:30
Jagannadha Sutradharudu Teki
2bf48026fd mtd: sf: Zap ramtron driver
Removed ramtron driver since the EMK boards are
no longer been active, and these are the only boards
used this flash driver.

Commit details for EMK zap:
"ppc/arm: zap EMK boards"
(sha1: d58a9451e7)

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
2014-12-18 18:17:54 +05:30
Steve Rae
0ff7e585df fastboot: handle flash write to GPT partitions
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Additionally, prepare and write the Backup GUID Partition Table.

Signed-off-by: Steve Rae <srae@broadcom.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Exynos4412 - Trats2]
2014-12-18 12:26:06 +01:00
Steve Rae
e1f6b0a02d disk: part_efi: move code to static functions
Signed-off-by: Steve Rae <srae@broadcom.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Exynos4412 - Trats2]
2014-12-18 12:26:06 +01:00
Przemyslaw Marczak
f597fc3d4c dfu: dfu_get_buf: check the value of env dfu_bufsiz before use
In function dfu_get_buf(), the size of allocated buffer could
be defined by the env variable. The size from this variable
was passed for memalign() without checking its value.
And the the memalign will return non null pointer for size 0.

This could possibly cause data abort, so now the value of var
is checked before use. And if this variable is set to 0 then
the default size will be used.

This commit also changes the base passed to simple_strtoul()
to 0. Now decimal and hex values can be used for the variable
dfu_bufsiz.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Przemyslaw Marczak
62a96d805f gadget: f_thor: check pointers before use in download_tail()
Some pointers in function download_tail() were not checked
before the use. This could possibly cause the data abort.
To avoid this, check if the pointers are not null is added.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Przemyslaw Marczak
7da6fa2716 dfu: mmc: check if mmc device exists in mmc_block_op()
The function mmc_block_op() is the last function before
the physicall data write, but the mmc device pointer is not
checked. If mmc device not exists, then data abort will occur.
To avoid this, first the mmc device pointer is checked.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Rob Herring
267abc626d fastboot: add support for continue command
The fastboot continue command is defined to exit fastboot and continue
autoboot. This commit implements the continue command and the exiting of
fastboot only. Subsequent u-boot commands can be processed after exiting
fastboot. Autoboot should implement a boot script such as "fastboot; mmc
read <...>; bootm" to fully implement the fastboot continue function.

Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:06 +01:00
Rob Herring
fe1b28c9f0 usb, g_dnl: generalize DFU detach functions
In order to add detach functions for fastboot, make the DFU detach related
functions common so they can be shared.

Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]
2014-12-18 12:26:05 +01:00
Tom Rini
e3bf81b1e8 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-12-16 15:20:02 -05:00
Bo Shen
68ae882596 USB: gadget: atmel_usba_udc: fix transfer hang issue
When receive data, the RXRDY in status register set by hardware
after a new packet has been stored in the endpoint FIFO. After,
we copy from FIFO, we clear it, make the FIFO can be accessed
again.
In the receive_data() function, this bit RXRDY has been cleared.
So, after the receive_data() function return, this bit should
not be cleared again, or else it will cause the accessing FIFO
corrupt, which will make the data loss.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2014-12-16 16:08:50 +01:00
Tom Rini
3bfbf32b6f Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-16 09:41:00 -05:00
Pavel Machek
065496d1b5 arm: socfpga: board: Repair Micrel PHY tuning
Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Pavel Machek <pavel@denx.de>
2014-12-16 15:32:14 +01:00
Tom Rini
b9206e61f3 Merge git://git.denx.de/u-boot-x86 2014-12-15 17:13:47 -05:00
Tang Yuantian
0023352855 mpc85xx/t104xrdb: convert deep sleep to generic board interface
A new interface is introduced to support generic board structure.
Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:17:12 -08:00
Zhao Qiang
9c7c86f431 qe/deep-sleep: modify qe deep-sleep for generic board
Deep sleep for generic board is supported now, modify qe
deep-sleep code to adapt it.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:49 -08:00
Tudor Laurentiu
d4be1753c6 p5040ds: changed liodn offsets
Offsets were overlaping, causing pamu access violations in
hypervised scenarios.

Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:34 -08:00
gaurav rana
851c9dbad2 crypto/fsl: Fix RNG instantiation failure.
Corrected the order of arguments in memset in run_descriptor
function. Wrong order of argumnets led to improper initialization
of members of struct type result. This resulted in RNG instantiation
error.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:26 -08:00
Jeffrey Ladouceur
2a8b34220d powerpc/T10xx: Fix number of portals
Following boards has incorrect number of portals defined.
powerpc/T102xQDS
powerpc/T102xRDB
powerpc/T1040QDS
powerpc/T104xRDB

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:17 -08:00
Jeffrey Ladouceur
3fa66db459 mpc85xx: inhibit qman and bman portals by default
Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:16:07 -08:00
Shengzhou Liu
24d827f526 net/fm: update ft_fixup_port to differentiate dual-role mac
we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:15:55 -08:00
York Sun
0ccee4e627 powerpc/mpc85xx: Fix DDR TLB mapping leftover
Commit f29f804a93 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
CC: Scott Wood <scottwood@freescale.com>
2014-12-15 09:15:40 -08:00
York Sun
938bbb6013 driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-15 09:15:12 -08:00
Shaohui Xie
84d13c5810 powerpc/p2041rdb: enable generic board configs
Add following configs in header file:
CONFIG_SYS_GENERIC_BOARD
CONFIG_DISPLAY_BOARDINFO

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:15:04 -08:00
Chunhe Lan
9a509cf66a powerpc/t4240rdb: Convert to use generic board code
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:14:58 -08:00
harninder rai
4aafbb4451 powerpc/bsc913x: Convert to use generic board code
Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:14:41 -08:00
Masahiro Yamada
7cbd74f748 ARM: remove redundant asmlinkage define
Use asmlinkage defined in include/linux/linkage.h if necessary.
Actually no ARM board uses asmlinkage, so this commit has no impact.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-12-15 07:22:56 -07:00
Masahiro Yamada
e6126a5872 x86: move arch-specific asmlinkage to <asm/linkage.h>
Commit 65dd74a674 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.

Commit ed0a2fbf14 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)

The generic asmlinkage is defined in <linux/linkage.h>.  If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-15 07:22:53 -07:00
Bin Meng
ba7b38a529 x86: Add a simple command to show FSP HOB information
FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.

Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:06 -07:00
Bin Meng
bceb9f0fc8 x86: Support Intel FSP initialization path in start.S
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:05 -07:00