Commit graph

56587 commits

Author SHA1 Message Date
Eugeniu Rosca
80281829a6 fdt: boot_get_fdt: simplify no_fdt handling (non-functional)
Increase the readability of boot_get_fdt().
No change in behavior is expected.

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 20:26:43 -06:00
Eugeniu Rosca
9ee9cf31ae fdt: boot_get_fdt: really boot w/o FDT when "goto no_fdt"
The 'no_fdt' goto label was introduced by v2015.01 commit [0] and it
had two review stages [1-2]. The *documented* purpose behind commit [0]
is (excerpt from commit description):

> allows both FDT and non-FDT kernels to boot by making the
> third parameter to the bootm/bootz optional

While [1] and [2] share the same goal, they have very different
implementations:
 - [1] was based on a very simple 'argc' check at function error out
   with returning success to the caller if the third parameter was NOT
   passed to bootm/bootz command. This approach had the downside of
   returning success to the caller even in case of legitimate internal
   errors, which should halt booting.
 - [2] added the "no_fdt" label and several "goto no_fdt" statements.
   This allowed to report the legitimate internal errors to the caller.

IOW the major difference between [1] and [2] is:
 - [1] boot w/o FDT if FDT address is not passed to boot{m,z,*}
 - [2] give *freedom* to the developer to boot w/o FDT from any
   (more or less) arbitrary point in the function flow (and here
   comes the peculiar aspect, which looks to be a leftover from [1])
   with the precondition that the 3rd argument (FDT address) is NOT
   provided to boot{m,z,*}. In practice, this means that only a subset
   of "goto no_fdt" end up booting w/o FDT while the other subset is
   returning an error to the caller.

This patch removes the peculiar behavior described above, such that
"goto no_fdt" performs really what it tells to the developer.

The motivation of this patch is to decrease the unneeded complexity
and increase the readability of boot_get_fdt().

[0] 48aead71c1 ("fdt: Allow non-FDT kernels to boot when CONFIG_OF_LIBFDT is defined")
[1] https://patchwork.ozlabs.org/patch/412923/
    ("[U-Boot,v1] fdt: Allow non-FDT kernels to boot when CONFIG_OF_LIBFDT is defined")
[2] https://patchwork.ozlabs.org/patch/415635/
    ("[U-Boot,v2] fdt: Allow non-FDT kernels to boot when CONFIG_OF_LIBFDT is defined")

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 20:26:43 -06:00
Eugeniu Rosca
d9313efc2e fdt: boot_get_fdt: remove redundant zeroing out
Paranoid programming [1] lies at the foundation of proper software
development, but the repetitive zeroing-out of output arguments in the
context of the same function rather clutters the code and inhibits
further refactoring/optimization than is doing any good.

In boot_get_fdt(), we already perform zero/NULL-initialization of
*of_flat_tree and *of_size at the beginning of the function, so doing
the same at function error-out is redundant/superfluous.

Moreover, keeping the code unchanged might encourage the developers to
update *of_flat_tree and *of_size during some interim computations,
which is against the current design of boot_get_fdt(). Currently,
writing useful data into these arguments happens just before
successfully returning from boot_get_fdt() and it should better stay so.

[1] https://blog.regehr.org/archives/1106

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 20:26:43 -06:00
Lars Povlsen
25c07c72fd ARMv8: PSCI: Fix PSCI_TABLE relocation issue
This fixes relaction isses with the PSCI_TABLE entries in
the psci_32_table and psci_64_table.

When using 32-bit adress pointers relocation was not being applied to
the tables, causing PSCI handlers to point to the un-relocated code
area. By using 64-bit data relocation is properly applied. The
handlers are thus in the "secure data" area, which is protected by
/memreserve/ in the FDT.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
2019-04-23 17:57:28 -04:00
Trent Piepho
b4353b3713 bootm: Simplying cache flush code
The cache flush of the kernel load area needs to be aligned outward to
the DMA cache alignment.  The operations are simpler if we think of this
as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and
aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find
the length of the flushed region by subtracting the former from the
latter.

Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:27 -04:00
Andreas Dannenberg
4c6be01c27 malloc: Fix memalign not honoring alignment prior to full malloc init
When using memalign() in a scenario where U-Boot is configured for full
malloc support with simple malloc not explicitly enabled and before the
full malloc support is initialized, a memory block is being allocated
and returned without the alignment parameter getting honored.

Fix this issue by replacing the existing memalign pre-full malloc init
logic with a call to memalign_simple() this way ensuring proper alignment
of the returned memory block.

Fixes: ee038c58d5 ("malloc: Use malloc simple before malloc is fully initialized in memalign()")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-04-23 17:57:27 -04:00
Stefan Roese
443b3ce5cf spl: spl_nand.c: Add NAND loading message
This patch adds a short message to the SPL NAND loader, which displays
the source and destinations addresses including the size of the
loaded image, like this:

U-Boot SPL 2019.04-rc3-00113-g486efd8aaf (Mar 15 2019 - 14:18:02 +0100)
Trying to boot from NAND
Loading U-Boot from 0x00040000 (size 0x000a0000) to 0x22900000

I find this message quite helpful - hopefully others do so as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:27 -04:00
Fabien Parent
def2fc05f6 ARM: MediaTek: Add support for MT8516 SoC
Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
6fdb50c098 pinctrl: add driver for MT8516
Add Pinctrl driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
cd52c3253a clk: mediatek: add driver for MT8516
Add clock driver for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
[trini: Redo whitespace]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
fe913a8bb6 clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:26 -04:00
Fabien Parent
b5096f1b6d mmc: mtk-sd: fix configuration option check
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO).
IS_ENABLE(FOO) will always return false.

This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO)
syntax.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
2019-04-23 17:57:25 -04:00
Fabien Parent
a93326681d mmc: mtk-sd: add support for MT8516
Add config for handling MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:25 -04:00
Fabien Parent
ba077e5f74 mmc: mtk-sd: add source_cg clock support
Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
2019-04-23 17:57:25 -04:00
Shawn Guo
7c798a11d4 poplar: enable Ethernet driver support
The 'phy' reset of gmac device in kernel device tree is not generic
enough for u-boot to use, so we need to overwrite the 'resets' property
as needed.  With this device tree fixup and poplar_defconfig changes,
Ethernet starts working on Poplar board.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:25 -04:00
Shawn Guo
1d5b5d2f8f net: add higmacv300 Ethernet driver for HiSilicon platform
It adds the driver for HIGMACV300 Ethernet controller found on HiSilicon
SoCs like Hi3798CV200.  It's based on a downstream U-Boot driver, but
quite a lot of code gets rewritten and cleaned up to adopt driver model
and PHY API.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Shawn Guo
f5e6c168c1 reset: add reset driver for HiSilicon platform
It adds a Driver Model compatible reset driver for HiSlicon platform.
The driver implements a custom .of_xlate function, and uses .data field
as reset register offset and .id field as bit shift.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Shawn Guo
f5ed7481e7 reset: add polarity field into struct reset_ctl
Some reset controllers support different polarities for reset operation,
so let's add a polarity field into struct reset_ctl.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 17:57:24 -04:00
Thierry Reding
aec4298ccb pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS
If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:23 -04:00
Thierry Reding
d94d9aa675 pci: Add boundary check for hose->regions
Make sure that we don't overflow the hose->regions array, otherwise we
would end up overwriting the hose->region_count field and cause mayhem
to ensue. Also print an error message when we'd be overflowing because
it indicates that there aren't enough regions available and the number
needs to be increased.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-04-23 17:57:23 -04:00
Adam Ford
248b873541 ARM: da850evm: Remove legacy MMC code
With the migration to DM in SPL and the DT support, the
old legacy code is no longer neaded, so this patch removes it

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-04-23 17:57:23 -04:00
Philippe Reynes
d6ce4c054a bcm963158: enable led support
Enable the led support in the configuration
of the board bcm963158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:23 -04:00
Philippe Reynes
4ae0542de7 dt: bcm963158: enable led controller
Enable the led controller in the device tree
of the board bcm963158.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
cfbb03be1c dt: bcm63158: add led controller
Add the led controller in the bcm63158 device tree.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
4ac59e3381 led: bcm6858: allow to use this driver on ARCH_963158
Allow the led bcm6858 driver to be used on bcm63158.
They have the same led controller.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
102b2317d8 bcm968580xref: enable led support
Enable the led support in the configuration
of the board bcm968580xref.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:22 -04:00
Philippe Reynes
9689921921 dt: bcm968580xref: enable led controller
Enable the led controller in the device tree
of the board bcm968580xref.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-04-23 17:57:14 -04:00
Christophe Kerello
c406a47431 mmc: stm32_sdmmc2: Fix r1b timeout issue
On response type r1b, if DTIME is not defined or too short,
the Datatimeout and DPSM flag occurs. Like the DPSM is
activated all next data transfer will be frozen.
To avoid this freeze:
    -The driver must define a DTIME on all r1b response type.
    -DTIME of SDMMC must be defined for alls stop transmission
     (for read and write request) even if MMC_RSP_BUSY is not set.
    -If busy timeout occur, an abort request must be sent to
     reinitialize the DPSM.

Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
2019-04-23 15:42:28 +02:00
Patrick Delaunay
b611535238 mmc: stm32_sdmmc2: Update DT properties with v4.19 bindings
Some properties name has been updated:
  - st,dirpol becomes st,sig-dir
  - st,negedge becomes st,neg-edge
  - st,pin-ckin becomes st,use-ckin

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:42:23 +02:00
Patrice Chotard
c89b87cbfc ARM: dts: stm32: Update sdmmc binding for stm32mp157c-ed1
Update some sdmmc properties which have been updated with
v4.19 DT bindings:
      - st,dirpol becomes st,sig-dir
      - st,negedge becomes st,neg-edge
      - st,pin-ckin becomes st,use-ckin

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:56 +02:00
Patrice Chotard
e4995e61c9 ARM: dts: stm32: Update sdmmc binding for stm32h743i-eval
Update some sdmmc properties which have been updated with
v4.19 DT bindings:
      - st,dirpol becomes st,sig-dir
      - st,negedge becomes st,neg-edge
      - st,pin-ckin becomes st,use-ckin

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:52 +02:00
Patrice Chotard
77594d7fbf board: stm32f746-disco: Get MII/RMII phy_mode from DT
This is needed to make ethernet work on stm32f746-eval which
uses MII mode.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-04-23 15:31:48 +02:00
Patrice Chotard
136580c1bb configs: stm32f746-disco: Enable SPI_FLASH_MACRONIX
This config file is shared between stm32f746-disco and stm32f769-disco.
These 2 boards doesn't embed the same qspi flash (Micron n25q128a on
f746-disco, Macronix mx66l51235l on f769-disco).

To be able to use Macronix mx66l51235l on F769-disco, flags
SPI_FLASH_MACRONIX must be enabled.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:44 +02:00
Patrice Chotard
cc19887de2 configs: stm32f746-disco: enable CONFIG_DISTRO_DEFAULTS
Allows to boot linux distribution

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:40 +02:00
Patrice Chotard
019ce052c8 configs: stm32f746-disco: update EXTRA_ENV_SETTINGS
Allows to boot linux distribution.

As stm32f746-disco and stm32f769-disco are sharing the same defconfig
file, in case of stm32f769-disco build, "fdtfile=..." must be updated
with the correct stm32f769 DTB file name.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:35 +02:00
Patrice Chotard
6f41d1a17e mmc: arm_pl180_mmci: Sync compatible with kernel
Initially the compatible string was wrongly set to "st,stm32f4xx-sdio".
Use compatible string used by kernel instead and identify mmci variant
using "arm,primecell-periphid" property.

Currently, the DM part of mmci driver is only used by STM32 SoCs,
that's why the switch case gets only one entry. It will be populated
easily with new variant in the future.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:30 +02:00
Patrice Chotard
dd18df440a pinctrl: stm32: Add st,stm32f769-pinctrl compatible string
Due to DT kernel synchronisation, add new pinctrl compatible
string for stm32f769.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:25 +02:00
Patrice Chotard
60121266c9 ARM: dts: stm32: Restore old usart1 clock bindings for stm32f7
As U-boot stm32f clock driver doesn't support new
bindings for auxiliary clocks (clocks = <&rcc 1 ....>),
restore old bindings for usart1 to get console output.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:21 +02:00
Patrice Chotard
13ba6d0e6f ARM: dts: stm32: Sync DT with v4.20 kernel for stm32h7
Synchronize stm32h7 device tree with kernel v4.20.
U-boot DT files and pinctrl bindings are updated,
useless nodes are removed and gpio compatible added.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:17 +02:00
Patrice Chotard
1056303148 ARM: dts: Migrate U-boot nodes to U-boot DT files for stm32h7
In order to prepare and ease future DT synchronization with kernel
DT, migrate all U-boot specific nodes/properties/addons to
U-boot DT files.

As sdmmc is not yet supported on kernel side, sdmmc nodes
are located in eval-u-boot and disco-u-boot DT files.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:11 +02:00
Patrice Chotard
fe63d3cfb7 ARM: dts: stm32: Sync DT with v4.20 kernel for stm32f7
Synchronize stm32f7 device tree with kernel v4.20.

All pinctrl bindings are updated.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:06 +02:00
Patrice Chotard
01aabf97d1 ARM: dts: stm32: Migrate U-boot nodes to U-boot DT files for stm32f7
In order to prepare and ease future DT synchronization with kernel
DT, migrate all U-boot specific nodes/properties/addons to
U-boot DT files.

Migrate also DT nodes which are not yet available on kernel DT side
as ethernet, ltdc and qspi nodes.

Fix ethernet_mii pins and add missing qspi_pins for stm32746g-eval

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:31:01 +02:00
Patrice Chotard
71dfd5f3f5 ARM: dts: stm32: Sync DT files with v4.20 kernel for stm32f4
Synchronize stm32f7 device tree with kernel v4.20.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:30:57 +02:00
Patrice Chotard
933f84cab9 ARM:dts: stm32: sort nodes by alphabetical order in f4 u-boot files
Sort nodes alphabetically to be coherent with all others STM32 DT files.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2019-04-23 15:30:52 +02:00
Neil Armstrong
c6e4e8f99c board: amlogic-q200: fix Khadas VIM2 README
The vendor U-boot branch and defconfig was wrong for the
Khadas VIM2, fix this.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:59 +02:00
Neil Armstrong
d714a5be8d board: amlogic: enable PHY_REALTEK for selected boards
When using the generic PHY on boards using an RGMII Realtek PHY,
gigabit speed is not always reliable.

This patch enables the Realtek PHY driver for such boards.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:49 +02:00
Jerome Brunet
b050a30016 boards: meson: add g12a u200
The Amlogic U200 board is based on the Amlogic S905D2 SoC
from the Amlogic G12A SoC family.

The board has the following specifications :
 - Amlogic S905D2 ARM Cortex-A53 quad-core SoC
 - XGB DDR4 SDRAM
 - 10/100 Ethernet (Internal PHY)
 - 1 x USB 3.0 Host
 - eMMC
 - SDcard
 - Infrared receiver
 - SDIO WiFi Module
 - MIPI DSI Connector
 - Audio HAT Connector
 - PCI-E M.2 Connector

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Neil Armstrong
f9e605437e ARM: dts: Import Amlogic G12A u200 DT from Linux 5.1-rc1
Import Linux 5.1-rc1 DT from 9e98c678c2d6 ("Linux 5.1-rc1") for the
meson-g12a-u200 board, the meson-g12a.dtsi and the corresponding bindings.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
17b7efe25b ARM: meson: add G12a support
Add support for the Amlogic G12A SoC, which is a mix between the
new physical memory mapping of AXG and the functionnalities of
the previous Amlogic GXL/GXM SoCs.

To handle the internal ethernet PHY, the Amlogic G12A SoCs now
embeds a dedicated PLL to feed the internal PHY.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00
Jerome Brunet
912af8423f clk: meson: add g12a support
Add basic support for the Amlogic G12A clock controller based on
the AXG driver.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-23 11:19:09 +02:00