A few boards still use ns16550_platdata structures, but assume the structure
is going to be in a specific order. By explicitly naming each entry,
this should also help 'future-proof' in the event the structure changes.
Tested on the Logic PD Torpedo + Wireless.
I only changed a handful of devices that used the same syntax as the Logic
board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods
and Alexander Graf.
Signed-off-by: Adam Ford <aford173@gmail.com>
V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c
V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c
V4: Fix subject heading
V3: Remove reg_offset out in all the structs. It was reverted out, and and if
it did exist, it would get initialized to 0 by default.
V2: I hastily copy-pasted the boards without looking at the UART number.
This addresses 3 boards that use UART3 and not UART1.
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Early system initialization is being done before initf_dm is being called
in U-Boot. Then system will fail to boot if any of the DM enabled driver
is being called in this system initialization code. So, rearrange the
code a bit so that DM enabled drivers can be called during early system
initialization.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
enables Self refresh mode by default and during warm reset the EMIF
contents are preserved. After warm reset EMIF sees that it is idle and
puts DDR in self-refresh. When in SR, leveling operations cannot be done
as DDR can only accept SR exit command, so its hanging during warm reset.
In order to fix this reset the power management control register before
EMIF initialization if it is a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
On DRA7, refresh ctrl shadow should be updated with
the final value.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Because KS2 u-boot works in 32 bit address space the existing ram_size
global data field cannot be used. The maximum, which the get_ram_size()
can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size
to fix up dtb.
This commit introduces the ddr3_get_size() which uses SPD data to
calculate the ddr3 size. This function replaces the "ddr3_size"
environment variable, which was used to get the SODIMM size.
For platforms, which don't have SODIMM with SPD and ddr3 is populated to
a board a simple ddr3_get_size function that returns ddr3 size has to be
implemented. See hardware-k2l.h
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.
The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The DSPs are powered on by default upon a Power ON reset, and
they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E
during the boot in u-boot. This is not functional on K2G though.
Extend the existing DSP power-off support to the only DSP present
on K2G. Do note that the PSC clock domain module id for DSP on K2G
differs from that of previous Keystone2 SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Define a macro for the DSP GEM power domain id number and
use it instead of a hard-coded number in the code that
disables all the DSPs on various Keystone2 SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is based on the davinci da850evm. It can boot from either the
on-board 16MB flash or from a microSD card. It also reads board
information from an I2C EEPROM.
The EV3 itself initally boots from write-protected EEPROM, so no
u-boot SPL is needed.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enable support for PMMC the TI power processor on K2G. This processor
manages all power management related activities on the SoC and and
allows the Operating Systems on compute processors such as ARM, DSP to
offload the power logic away into the power processor. U-boot just has a
load responsibility, hence the view of the hardware from a bootloader
perspective is different from the view of hardware from a Operating
System perspective. While bootloader just loads up the firmware,
Operating Systems look at the resultant system as "hardware".
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
These are useful for modules that need to be held in reset and are
enabled for data to be loaded on to them. Typically these are
microcontrollers or other processing entities in the system.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
'#define X a | b' is better defined as '#define X (a | b)' for obvious
reasons.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
u-boot coding style guidance in
http://www.denx.de/wiki/U-Boot/CodingStyle clearly mentions that the
kernel doc style shall be followed for documentation in u-boot.
Current PSC documentation standard does not, so fix that.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
With commit fe772ebd28 ("ARM: keystone2: Use common definition for
clk_get_rate"), we have centralized the clock code into a common clock
logic and the redundant files, unfortunately remained... Clean that
up.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).
The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI,
machine vision, networking, medical imaging and many other industrial
applications. This EVM is based on the same BeagleBoard-X15 Chassis
and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's
wlink8 offering.
Since the EEPROM contents are compatible between the BeagleBoard-X15 and
the AM57xx-evm, we add support for the detection logic to enable
support for various user programmable scripting capability.
NOTE: U-boot configuration is currently a superset of AM57xx evm and
BeagleBoard-X15 and no additional configuration tweaking is needed.
This change also sets up the stage for future support of TI AM57xx EVMs
to the same base bootloader build.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Many TI EVMs have capability to store relevant board information
such as DDR description in EEPROM. Further many pad configuration
variations can occur as part of revision changes in the platform.
In-order to support these at runtime, we for a board detection hook
which is available for override from board files that may desire to do
so.
NOTE: All TI EVMs are capable of detecting board information based on
early clocks that are configured. However, in case of additional needs
this can be achieved within the override logic from within the board
file.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have a generic TI eeprom logic which can be reused across
platforms, reuse the same.
This revision also includes fixes identified by Dave Gerlach
<d-gerlach@ti.com>
Cc: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Steven Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Use the generic EEPROM detection logic instead of duplicating the AM
eeprom logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Steven Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Several TI EVMs have EEPROM that can contain board description information
such as revision, DDR definition, serial number, etc. In just about all
cases, these EEPROM are on the I2C bus and provides us the opportunity
to centralize the generic operations involved.
The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM,
AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format.
However, DRA-7* EVMs, OMAP4SDP use a modified format.
We hence introduce logic which is generic between these platforms
without enforcing any specific format. This allows the boards to use the
relevant format for operations that they might choose.
This module will compile for all TI SoC based boards when
CONFIG_TI_I2C_BOARD_DETECT is enabled to have optimal build times for
platforms that require this support.
It is important to note that this logic is fundamental to the board
configuration process such as DDR configuration which is needed in
SPL, hence cannot be part of the standard u-boot driver model (which
is available later in the process). Hence, to aid efficiency, the
eeprom contents are copied over to SRAM scratchpad memory area at the
first invocation to retrieve data.
To prevent churn with cases such as DRA7, where eeprom format maybe
incompatible, we introduce a generic common format in eeprom which
is made available over accessor functions for usage.
Special handling for BBG1 EEPROM had to be introduced thanks to the
weird eeprom rev contents used.
The follow on patches introduce the use of this library for AM335x,
AM437x, and AM57xx.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Centralize gpi2c_init into omap_common from the sys_proto header so
that the information can be reused across SoCs.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Early clock initialization is currently done in two stages for OMAP4/5
SoCs. The first stage is the initialization of console clocks and
then we initialize basic clocks for functionality necessary for SoC
initialization and basic board functionality.
By splitting up prcm_init and centralizing this clock initialization,
we setup the code for follow on patches that can do board specific
initialization such as board detection which will depend on these
basic clocks.
As part of this change, since the early clock initialization
is centralized, we no longer need to expose the console clock
initialization.
NOTE: we change the sequence slightly by initializing console clocks
timer after the io settings are complete, but this is not expected
to have any functioanlity impact since we setup the basic IO drive
strength initialization as part of do_io_settings.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.
Move these options to Kconfig and tidy up board configuration:
CONFIG_FIT
CONFIG_OF_BOARD_SETUP
CONFIG_OF_SYSTEM_SETUP
CONFIG_FIT_SIGNATURE
CONFIG_FIT_BEST_MATCH
CONFIG_FIT_VERBOSE
CONFIG_OF_STDOUT_VIA_ALIAS
CONFIG_RSA
Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.
Note: Masahiro's moveconfig.py script is amazing.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to
do TMDS software reset and write to clear fc_invidconf register.
We need minimum 3 times to write to clear the fc_invidconf
register, so choose 5 loops here.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
LVDS have a different display out mode, add code to get right flag.
The vop_ip decide display device and the remote_vop_id decide which
vop was being used. So we should use the remote_vop_id to set DCLK_VOP.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some Rockchip SoCs support LVDS output. Add a display driver for this so
that these displays can be used on supported boards.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
Kconfig options must defined in the defconfig files. Since RSA_SOFTWARE_EXP
relies on CONFIG_DM, unless it is set in kconfig we cannot enable RSA.
Remove the hacks which enable CONFIG_DM in header files and update the
defconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2,
and it expects uboot to store the value using a same protocol. But now
the ddr setting value is different with DMC, so if you enable the DMC,
system would crash in kernel. Correct the sdram setting here, according
to the requirements of kernel.
[0]
https://chromium.googlesource.com/chromiumos/third_party/kernel/+/
chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
on v2016.03-rc3, size of SPL image compiled by gcc 5.3.0 is too large for
Firefly-RK3288. (it's fine for Rock2)
$ gcc --version
gcc (Ubuntu/Linaro 5.3.0-3ubuntu1~14.04) 5.3.0 20151204
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ ./tools/mkimage -n rk3288 -T rksd -d spl/u-boot-spl-dtb.bin u-boot-spl-dtb.img
Warning: SPL image is too large (size 0x80d0) and will not boot
to reduce size of SPL image, this patch makes configure_emmc() empty for
Firefly-RK3288 as same as Rock2.
Signed-off-by: FUKAUMI Naoki <naobsd@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-By: Vagrant Cascadian <vagrant@debian.org>
emac may use dpll as clock parent, and it request the clock frequency
multiples of 50, so change ddr frequency to 400M.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Now that we fall back to the FS code path when we don't find u-boot
at the raw sector offset, there is no good reason to not default to
raw boot.
With this patch, I can successfully boot u-boot from a raw sector
offset on beagle-xm.
Signed-off-by: Alexander Graf <agraf@suse.de>
This function should just return for unknown SoCs rather than writing
unexpected values to registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
During very early boot-ROM execution the pinmux
configuration isi in Hi-Z state. If pull-up is enabled
on GPIO pad's there will be a short period of toggle
from high to low on the IO when GPIO is set low during
boot. To avoid this glitch, disable pull-up configuration
in GPIO pinmux.
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
This introduces some minor cleanups, regarding aspects such as board name, code
and headers organization as well as deprecated and missing config options.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The UniPhier SoC family has not supported ARMv8 yet, but these would
cause warnings if they were compiled with a 64bit compiler. Before
adding the ARMv8 support really, fix them now.
Because UniPhier SoCs do not support Large Physical Address Extension,
casting "phys_addr_t" into "unsigned long" would carry the address
as is.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Before adding ARMv8 support, this commit refactors the directory
structure. Move ARMv7 specific files to arch/arm/mach-uniphier/arm32
to avoid a mess by mixture of ARMv7 and ARMv8 code. Also move the
"select CPU_V7" to the lower-level menu because we will have to
select ARM64 instead of CPU_V7 for ARMv8 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Due to the company's awful projecting, PH1-LD10 and PH1-sLD11 have
been renamed to PH1-LD20 and PH1-LD11, respectively.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The chains of "depends on <SoC_name>" in the current Kconfig is
clumsy. The idea here is to allow users to choose a SoC group first
(SoC group consists of some SoCs that can coexist in one binary).
Then, allow to enable/disable each SoC support in the selected SoC
group. This makes the Kconfig menu clearer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These macros are no longer used. These base addresses are
SoC-dependent, so they should not be placed in the header.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, DRAM size is converted twice:
size in byte -> size in Gbit -> enum
Optimize the code by converting the "size in byte" into enum directly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The if-else statements for the frequency-dependent register settings
seem clumsy. Moving them to arrays would make it cleaner.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The DDR PHY settings no longer depend on the DRAM size. Drop the
argument from the init function.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now these three are almost the same. The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored. (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add a field to distinguish DDR3+ from (standard) DDR3. It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).
Default DDR3 spec for each SoC:
PH1-LD4, PH1-sLD8: DDR3+
Others: DDR3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These settings control the clocks around the memory controller.
The debug ability is unneeded once it works properly.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
These settings were used only for the PH1-sLD3 and older SoCs. The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, a dummy value is defined for the UMC_SPCCTLA register
when the DRAM size is zero. This seems weird because the controller
does not need setting in the first place if the size is zero.
Also, redefine enum dram_size to represent the DRAM size per 16-bit
unit. This makes things simpler because the channel 0 and 1 are
connected with 32-bit width DRAM, while the channel 2 is connected
with 16-bit width one.
I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_*
for consistency) while I am here because SIZE_* might be easily
mixed-up with the macros in include/linux/sizes.h.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it. It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Of the several boot devices supported, it looks like the eMMC is the
most commonly used. Enable CONFIG_ENV_IS_IN_MMC by default.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
UniPhier SoC family supports both (e)MMC boot and SD card boot;
however, both of them are handled in the same uclass.
When booting from the eMMC, we want to know the device number
of the (e)MMC, not SD. This command is useful to find the first
MMC (non-SD) device.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Export device nodes needed for eMMC boot (eMMC node, pinctrl, and
clock) to the SPL DTB. CONFIG_SUPPORT_EMMC_BOOT is also necessary
to use "mmc partconf" command.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Enable the driver in all UniPhier defconfig files and add some
needed defines to the common files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
I implemented a GPIO driver based on Driver Model for the UniPhier
SoC family, but I could not find any good reason why such SoC
specific GPIO headers are needed.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
Gets propagated into the device tree and then into /proc/cpuinfo where
users often expect it.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
Base addresses for GPIOs could be different for different socs, this
patch moves the base addresses from driver to the soc specific location.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
This patch removes the gpio clock enable from gpio driver & move it in the
board code, making it possible to use the gpio driver with other socs.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
The following patch caused cpu_eth_init() to not be called anymore
for DM-capable boards:
commit c32a6fd07b
Date: Sun Jan 17 14:51:56 2016 -0700
net: Don't call board/cpu_eth_init() with driver model
This breaks ethernet on SoCFPGA, since we use that function to un-reset
the ethernet blocks. Invoke the ethernet reset function from arch_misc_init()
instead to fix the breakage.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
Weed out bashisms from the script. The echo -e does not work in dash,
which is the default /bin/sh in debian .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
The initialization for smmu and stream id is moved into the common soc
code.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart
to driver model suport. Enable lpuart port driver.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
Add support for phy 1-3.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Split duart configuration as device tree file. Move /chosen node
out of board commone device tree. Convert ls1021aqds nor and SD
configurations to driver model support (qspi already uses DM).
Enable ns16550 DM serial driver for nor configurations.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alison Wang <alison.wang@nxp.com>
DTS syncup with Linux kernel.
Add missing reset-gpio property.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable u-boot,dm-pre-reloc for qspi for zc706, zed and microzed.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove unused macros. Adresses are taken from DT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals affected by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is to set the peripherals to Domain0 by A core, since A core
in Domain0. The peripherals which will be used by M4, will be set to Domain1
by M4.
For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
set WDOG4 to domain1, because M4 will use WDOG4.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.
This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.
arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
