Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-11 15:37:23 +00:00
Code Issues Projects Releases Packages Wiki Activity

gpio: stm32_gpio: move base addresses to the soc file

Browse source 
Base addresses for GPIOs could be different for different socs, this
patch moves the base addresses from driver to the soc specific location.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
This commit is contained in:
Vikas Manocha 2016-02-11 15:47:18 -08:00 committed by Tom Rini
parent 14cec06113
commit 09959ba3c5
3 changed files with 18 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
arch/arm/include/asm/arch-stm32f1/stm32.h
View file

@ -24,6 +24,14 @@
#define STM32_BUS_MASK 0xFFFF0000
#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
/*
* Register maps
*/

10
arch/arm/include/asm/arch-stm32f4/stm32.h
View file

@ -23,6 +23,16 @@
#define STM32_BUS_MASK 0xFFFF0000
#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
/*
* Register maps
*/

18
drivers/gpio/stm32_gpio.c
View file

@ -20,16 +20,6 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_STM32F4)
#define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000)
#define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400)
#define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800)
#define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00)
#define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000)
#define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400)
#define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800)
#define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00)
#define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000)
static const unsigned long io_base[] = {
STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
@ -85,14 +75,6 @@ out:
return rv;
}
#elif defined(CONFIG_STM32F1)
#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800)
#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00)
#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000)
#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400)
#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800)
#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00)
#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000)
static const unsigned long io_base[] = {
STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,