Commit graph

699 commits

Author SHA1 Message Date
Simon Glass
51de94dfe4 x86: coral: Allow init of debug UART in U-Boot proper
At present the debug UART is only set up in SPL, on the assumption that
the boot flow will always pass through there. When booting from coreboot,
SPL is not used, so the debug UART is not available.

Move the code into a common place so that it can be used in U-Boot proper
also. Add the required init to start_from_spl.S as well.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:30 +13:00
Simon Glass
e7bae8283f x86: Allow installing an e820 when booting from coreboot
Move this code into a generic location so that it can be used by other x86
boards which want to boot from coreboot. Also ensure that this is called
if booting from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 15:04:29 +13:00
Simon Glass
1058ab37f7 x86: coreboot: Update parsing of the latest sysinfo
Quite a few new tag types have been added over the years. Bring these into
U-Boot so that all required tags can be parsed.

Add a proper comment to struct sysinfo_t while we are here, since many of
the meanings are not obvious.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:59 +13:00
Simon Glass
f9f06e628e x86: coreboot: Sync up timestamp codes
Add new timestamp codes that are present in coreboot, so that we can decode
these in U-Boot.

At present TS_U_BOOT_START_KERNEL is used twice. It should only be used
just before jumping to Linux, so update the other call site to use
TS_START_KERNEL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
17753b0382 x86: Move coreboot timestamp info into coreboot_tables.h
This all relates to the sysinfo structure provided by coreboot. Put the
timestamp definitions into the same file as the others. Tidy up a few
comments at the same time.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Simon Glass
e35b6497f4 x86: Make coreboot sysinfo available to any x86 board
It is possible to boot U-Boot for chromebook_coral either 'bare metal' or
from coreboot. In the latter case we want to provide access to the coreboot
sysinfo tables. Move the definitions into a file available to any x86
board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-27 13:59:37 +13:00
Tom Rini
22fc991daf Prepare v2021.04-rc4
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Merge tag 'v2021.04-rc4' into next

Prepare v2021.04-rc4
2021-03-15 12:15:38 -04:00
Simon Glass
0b823e16b6 x86: Fix member check in intel_gnvs
When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it.

Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-03-09 09:42:12 +08:00
Simon Glass
edab114775 gpio: x86: Drop the deprecated methods in intel_gpio
We don't need to implement direction_input() and direction_output()
anymore. Drop them and use update_flags() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-03 15:40:11 -05:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Simon Glass
577c4ad055 x86: zimage: Allow dumping the image from outside the module
At present it is possible to dump an image within the zimage command, but
it is also useful to be able to dump it from elsewhere, for example in a
loader that has special handling for the different zimage stages.

Export this feature as a new function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01 15:33:25 +08:00
Simon Glass
f82438948f x86: Update Chromium OS GNVS names
The Global Non-Volatile Storage struct has some fields with particular
meanings. Rename these to make things easier to follow. Also add a few
more boot flags.

GNVS should not be confused with GNVQ (Going Nowhere Very Quickly).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-02-01 15:33:24 +08:00
Simon Glass
442e6305b5 x86: coral: Support TPM and RTC in SPL
Update the devicetree so that the TPM and RTC can be used in SPL. Also
enable the pins used for getting the memory configuration settings while
we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-30 14:25:41 -07:00
Simon Glass
21303d1de7 x86: apl: Adjust how the UART gets its platform data
At present this driver calls malloc() to start a new platform data
structure, fills it in and tells driver model to use it.

We want to avoid malloc, particularly with the new version of of-platdata.
Create a new struct which encompasses both the dtd struct and the ns16550
one, to avoid this. Unfortunately we must copy the data into the right
place for the ns16550 driver. Add some comments about this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:41 -07:00
Simon Glass
6a2350f8c9 x86: sysreset: Move priv/plat structs to headers
With the new of-platdata, these need to be available to dt_platdata.c
so must be in header files. Move them and add the dtd struct too.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2021-01-05 12:24:41 -07:00
Simon Glass
f6257f7914 x86: Move priv/plat structs for intel_common to headers
With the new of-platdata, these need to be available to dt_platdata.c
so must be in header files. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:41 -07:00
Simon Glass
366c4eb4b5 x86: apl: Move priv/plat structs to headers
With the new of-platdata, these need to be available to dt_platdata.c
so must be in header files. Move them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:41 -07:00
Simon Glass
941e6304f4 x86: Fix header guard in asm/pmu.h
This has the wrong name. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:41 -07:00
Sughosh Ganu
ab201a116f fsp: Move and rename fsp_types.h file
The fsp_types.h header file contains macros for building signatures of
different widths. These signature macros are architecture agnostic,
and can be used in all places which use signatures in a data
structure. Move and rename the fsp_types.h under the common include
header.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-12-31 14:41:31 +01:00
Simon Glass
df3dc20952 x86: Drop unnecessary mp_init logic
Now that sequence numbers are set up when devices are bound, this code is
not needed. Also, we should use dev_seq() instead of req_seq. Update the
whole file accordingly.

Also fix up APL cpu while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Simon Glass
8a8d24bdf1 dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
d1998a9fde dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
caa4daa2ae dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:08 -07:00
Simon Glass
96d0aa9143 x86: Use CONFIG_CHROMEOS_VBOOT for verified boot
At present CONFIG_CHROMEOS is used to determine whether verified boot is
in use. The code to implement that is not in U-Boot mainline.

However, it is useful to be able to boot a Chromebook in developer mode
in U-Boot mainline without needing the verified boot code.

To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot
should be used, and CONFIG_CHROMEOS to indicate that the board supports
Chrome OS. That allows us to define CONFIG_CHROMEOS on coral.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:31 +08:00
Simon Glass
08059c9c02 x86: Define the Chrome OS GNVS region
It is not possible to boot Chrome OS properly without passing some basic
information from U-Boot. This applies even if verified boot is not being
used. Add a structure definition for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:31 +08:00
Simon Glass
a0ed800376 x86: Show the interrupt pointer with 'irqinfo'
It is useful for this command to show the address of the interrupt table.
Add support for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-06 09:51:29 +08:00
Simon Glass
38e498c3a2 x86: Allow writing tables to fail
At present write_tables() can fail but does not report this problem to its
caller. Fix this by changing the return type.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
dac7778d74 x86: Add a layout for Chrome OS verified boot
Add definitions for part of the vboot context used with verified boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
6571d87315 x86: apl: Add core init for the SoC
Set up MSRs required for Apollo Lake. This enables Linux to use the
timers correctly. Also write the fixed MSRs for this platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 14:58:45 +08:00
Simon Glass
29d2d64ed5 x86: Add support for more than 8 MTRRs
At present the mtrr command only support 8 MTRRs. Some SoCs have more than
that. Update the implementation to support up to 10. Read the number of
MTRRs dynamically instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
10536ceae9 x86: hob: Try to show a name instead of a GUID
GUIDs are one of the seven evils of the computer world. They obfuscate the
meaning and require people to look up long hex strings to decode it.

Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use.

Add a way to decode the GUIDs known to U-Boot. Add a few more to the list
for good measure.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:27 +08:00
Simon Glass
26c3d3d7d5 x86: Add a header guard to asm/acpi_table.h
This file cannot currently be included in ASL files. Add a header guard
to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
3a25073a40 x86: Correct the assembly guard in e820.h
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:22 +08:00
Simon Glass
aec7c1c565 x86: cpu: Report address width from cpu_get_info()
Add support for this new field in the common code used by most x86 CPU
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:21 +08:00
Simon Glass
c90b302d5f x86: fsp: Update the FSP API with the end-firmware method
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.

Add a definition for this new method and update the comments a little.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-09-25 11:27:21 +08:00
Simon Glass
da2c1b8fd9 x86: apl: Generate required ACPI tables
Add support for generating various ACPI tables for Apollo Lake. Add a few
S3 definitions that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
94c5ad2534 x86: apl: Allow reading hostbridge base addresses
Add a few functions to permit reading of various useful base addresses
provided by the hostbridge.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
540f0bae9b x86: acpi: Add support for additional Intel tables
Apollo Lake needs to generate a few more table types used on Intel SoCs.
Add support for these into the x86 ACPI code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:19 +08:00
Simon Glass
9b3e6d4c1f x86: acpi: Add common Intel ACPI tables
Add various tables that are common to Intel CPUs. These functions can be
used by arch-specific CPU code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
7764a8481c x86: acpi: Add PCT and PTC tables
These are needed for the CPU tables. Add them into an x86-specific file
since we do not support them on sandbox, or include tests.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:18 +08:00
Simon Glass
f37979e7b7 x86: acpi: Support generation of the DBG2 table
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.

Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:17 +08:00
Simon Glass
d2628984b7 x86: acpi: Support generation of the HPET table
Add an implementation of the HPET (High Precision Event Timer) ACPI
table. Since this is x86-specific, put it in an x86-specific file

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:17 +08:00
Simon Glass
6c0da2da7c x86: Add a few common Intel CPU functions
Add functions to query CPU information, needed for ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
abc585b745 x86: apl: Update iomap for ACPI
Add some more definitions to the iomap. These will be used by
ACPI-generation code as well as the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
10552377d4 x86: apl: Add power-management definitions
Add SCI and power-state definitions required by ACPI tables. Fix the
license to match the original source file.

Als update the guard on acpi_pmc.h to avoid an error when buiding ASL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
59561c7c2e x86: Add some definitions for SMM
U-Boot does not support SMM (System Management Mode) at present, but needs
a few definitions to correctly set up the ACPI table. Add these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:16 +08:00
Simon Glass
c9cc37de2c x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
e4f09f97c9 x86: Add wake sources for the acpi_gpe driver
Some devices can wake the system from sleep, e.g opening the lid on a
clamshell or moving a USB mouse.

Add a wake to specify this for USB devices and add the settings for Apollo
Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:15 +08:00
Simon Glass
7924b499a2 x86: acpi: Expand the GNVS
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00
Simon Glass
55109f1d4e x86: acpi: Support external GNVS tables
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.

Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-25 11:27:13 +08:00