Commit graph

34 commits

Author SHA1 Message Date
Bin Meng
ae2d9506a3 riscv: sifive: Rename fu540 board to unleashed
In preparation to add SiFive Unmatched board support, let's rename
the existing fu540 board to unleashed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-04-08 15:37:29 +08:00
Simon Glass
65e25bea59 dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()
In the spirit of using the same base name for all of these related macros,
rename this to have the operation at the end. This is not widely used so
the impact is fairly small.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:26:35 -07:00
Pragnesh Patel
f517e5fe98 riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller
Enable support for SiFive FU540 Opencores I2C master controller.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-11-28 08:30:41 +01:00
Bin Meng
3581811dc2 riscv: sifive/fu540: Move SPL related functions to spl.c
It's better to keep all SPL related functions in the same spl.c.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
50856c3f0f riscv: sifive/fu540: Drop NET_RANDOM_ETHADDR
This option was enabled during the earlier U-Boot porting time. Now
we already have the OTP driver in place and the unique MAC address
is read from the OTP, there is no need to turn on this option.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
ff8e88a6d7 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level
All FU540 driver related options should be in the SoC level Kconfig.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
d6a01704b0 riscv: sifive/fu540: spl: Rename soc_spl_init()
spl_soc_init() seems to be a better name, as all SPL functions
names start from the spl_ prefix.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
c4295ec849 riscv: sifive/fu540: spl: Drop our own version of board_init_f()
Use the generic board_init_f() provided by the RISC-V library codes.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-08-14 14:38:53 +08:00
Bin Meng
265d46ba13 Revert "Revert "riscv: sifive: fu540: Add gpio-restart support""
This reverts commit 23da3c682a.

Now the build failure of sifive_fu540_defconfig board has been fixed,
revert this "revert patch".

Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-07-24 14:55:31 +08:00
Jagan Teki
662d518e8a sifive: fu540: Mark the default env as SPI flash
Mark the default U-Boot environment as SPI flash since
this is an on board flash device.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24 14:55:19 +08:00
Jagan Teki
868e295ef7 sifive: fu540: Add runtime boot mode detection
Add support to detect boot mode at runtime for
SiFive FU540 boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24 14:55:19 +08:00
Pragnesh Patel
3d5ac3536b riscv: sifive: fu540: Enable SiFive PWM driver
This patch enables SiFive PWM driver for the SiFive
Unleashed board.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-24 14:55:11 +08:00
Tom Rini
23da3c682a Revert "riscv: sifive: fu540: Add gpio-restart support"
As part of merging the next branch in to master, the sifive_fu540 will
fail to link:
riscv64-linux-ld.bfd: lib/built-in.o: in function `panic_finish':
lib/panic.c:28: undefined reference to `do_reset'
make[2]: *** [spl/u-boot-spl] Error 1
make[1]: *** [spl/u-boot-spl] Error 2
make: *** [sub-make] Error 2

And while the "fix the build" option of enabling CONFIG_SPL_SYSRESET may
solve the issue, it is unclear that it is the correct path exactly.  For
the moment, I am reverting this commit and take a "revert the revert"
and proper fix as soon as it's available.

This reverts commit cdae446461.

Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-06 17:57:47 -04:00
Pragnesh Patel
5ce50206ed riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-03 15:09:06 +08:00
Bin Meng
cdae446461 riscv: sifive: fu540: Add gpio-restart support
The HiFive Unleashed board wires GPIO pin#10 to the input of the
system reset signal. This adds gpio reboot support.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-03 15:07:54 +08:00
Jagan Teki
085cb1d5d0 sifive: fu540: Add sample SD gpt partition layout
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.

partition layout:

Part    Start LBA       End LBA         Name
        Attributes
        Type GUID
        Partition GUID
  1     0x00000022      0x00000821      "loader1"
        attrs:  0x0000000000000000
        type:   5b193300-fc78-40cd-8002-e86c45580b47
        guid:   cbcbef44-e627-42bc-b134-93b6f3784b8c
  2     0x00000822      0x00002821      "loader2"
        attrs:  0x0000000000000000
        type:   2e54b353-1271-4842-806f-e436d6af6985
        guid:   f54eba28-d8de-4852-978d-1a673777e2ae
  3     0x00002822      0x00020821      "rootfs"
        attrs:  0x0000000000000004
        type:   0fc63daf-8483-4772-8e79-3d69d8477de4
        type:   linux
        guid:   9561df46-8d55-4799-a83b-cfee9ef6ff93

Note:
- loader1 would be fsbl or spl
- loader2 would be U-Boot or U-Boot proper

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
01cdef22ee riscv: sifive: fu540: add SPL configuration
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.

SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
7c45fc9870 riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
c514a94abf sifive: fu540: add ddr driver
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04 09:44:08 +08:00
Pragnesh Patel
88eec6159a riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Use the OTP DM driver to set the serial environment variable.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Tom Rini
e836a71b70 fu540: Remove ARCH= references from documentation
When building U-Boot we select the architecture via Kconfig and not ARCH
being passed in via the environment or make cmdline.

While in here, add the doc file to the MAINTAINERS entry.

Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-02 17:27:04 -04:00
Pragnesh Patel
4ef196ce20 sifive: fix palmer's email address
Fix Palmer's email address

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-05-26 15:50:15 +08:00
Simon Glass
eb41d8a1be common: Drop linux/bug.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
0914011310 command: Remove the cmd_tbl_t typedef
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:55 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Jagan Teki
286bcdb40f sifive: fu540: Enable spi-nor flash support
HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.

Tested on SiFive FU540 board.

Thanks to Sagar for various use cases and tests.

[QUAD mode in dt with spi-tx-bus-width: <4>]
 pp opcode      = 0x34 [QUAD MODE]
 read opcode  = 0x6c  [QUAD MODE]
 erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode     = 0x12 [SPI MODE]
read opcode  = 0xc   [SPI MODE]
erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30 22:34:20 +05:30
Sagar Shrikant Kadam
b332a89799 configs: fu540: enable gpio driver
Enable the DM based GPIO driver for FU540-C000 SoC.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-18 09:04:08 +08:00
Sagar Shrikant Kadam
cba0635386 riscv: sifive: fu540: set serial environment variable from otp
This patch sets the serial# environment variable by reading the
board serial number from the OTP memory region.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:29:54 +08:00
Bhargav Shah
0b96a761c5 riscv: sifive: fu540: Enable SiFive SPI and MMC SPI drivers
This patch enables SiFive SPI and MMC SPI drivers for the
SiFive Unleashed board.

Signed-off-by: Bhargav Shah <bhargavshah1988@gmail.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-07-19 14:25:06 +08:00
Anup Patel
9f2a0c0f38 riscv: sifive: fu540: Setup ethaddr env variable using OTP
This patch extends SiFive FU540 board support to setup ethaddr
env variable based on board serialnum read from OTP.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:52 +08:00
Anup Patel
8633edeb2a clk: sifive: Drop GEMGXL clock driver
The GEMGXL clock driver is now directly part of Cadence MACB
ethernet driver in upstream Linux kernel. There is no separate
GEMGXL clock driver in upstream Linux kernel hence we drop
GEMGXL clock driver from U-Boot as well.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-19 14:24:51 +08:00
Bin Meng
776d39d9a1 riscv: sifive: fu540: Enable GEMGXL MGMT driver
Enable the new GEMGXL MGMT driver so that GEM 10/100 Mbps works now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Tested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-06-01 13:33:17 -05:00
Lukas Auer
0ed93a8c59 riscv: fu540: enable SMP
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-08 09:44:26 +08:00
Anup Patel
3fda0262c3 riscv: Add SiFive FU540 board support
This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-27 09:12:33 +08:00