When boot from SRIO, slave's core can be in holdoff after powered on for
some specific requirements. Master can release the slave's core at the
right time by SRIO interface.
Master needs to:
1. Set outbound SRIO windows in order to configure slave's registers
for the core's releasing.
2. Check the SRIO port status when release slave core, if no errors,
will implement the process of the slave core's releasing.
Slave needs to:
1. Set all the cores in holdoff by RCW.
2. Be powered on before master's boot.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
For the master module, need to finish these processes:
1. Initialize the SRIO port and address space.
2. Set inbound SRIO windows covered slave's u-boot image stored in
master's NOR flash.
3. Master's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_MASTER_config
4. Master must boot first, and then slave can be powered on.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Currently "u-boot", the elf file generated via u-boot-nand.lds does not
contain required debug information i.e. .debug_{line, info, abbrev, aranges,
ranges} into their respective _global_ sections.
The original ld script line arch/powerpc/cpu/mpc85xx/start.o
KEEP(*(.bootpg)) is not entirely correct because the start.o file is already
processed by the linker,therefore the file wildcard in "KEEP(*(.bootpg))" will
not process start.o again for bootpg.
So Fix u-boot-nand.lds to generate these debug information.
Signed-off-by: Anmol Paralkar <b07584@freescale.com>
Signed-off-by: John Russo <John.Russo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
NAND SPL code never compile the vector table.
So no need to setup interrupt vector table for NAND SPL.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
After relocation of vector table in SDRAM's lower address, IVORs value should
be updated with new handler addresses.
As vector tables are relocated to 0x100,0x200... 0xf00 address in DDR.IVORs
are updated with 0x100, 0x200,....f00 hard-coded values.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
For e500 and e500v2 architecturees processor IVPR address should be alinged on
64K boundary.
in start.S, CONFIG_SYS_MONITOR_BASE is stored blindly in IVPR assuming it to be
64K aligned. It may not be true always. If it is not aligned, IVPR + IVORs may
not point to an exception handler.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This is useful for boards which cannot be reset in the usual way for the
85xx CPU. An example is a board which can only be reset by a hardware
watchdog.
Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The localbus controller node in the device tree is typically a root node,
even though the controller is part of CCSR. If we were to put the lbc
node under the SOC node, then the 'ranges' property in the lbc node would
translate through the 'ranges' property of the parent SOC node, and we
don't want that.
Since the lbc is a separate node, it's possible for the 'reg' property to
be wrong. This happened with the original version of p1022ds.dts, which
used a 32-bit value in the 'reg' address, instead of a 36-bit address.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Several macros are used to identify and locate the microcode binary image
that U-boot needs to upload to the QE or Fman. Both the QE and the Fman
use the QE Firmware binary format to package their respective microcode data,
which is why the same macros are used for both. A given SOC will only have
a QE or an Fman, so this is safe.
Unfortunately, the current macro definition and usage has inconsistencies.
For example, CONFIG_SYS_FMAN_FW_ADDR was used to define the address of Fman
firmware in NOR flash, but CONFIG_SYS_QE_FW_IN_NAND contains the address
of NAND. There's no way to know by looking at a variable how it's supposed
to be used.
In the future, the code which uploads QE firmware and Fman firmware will
be merged.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default. So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum A-003474: Internal DDR calibration circuit is not supported
Impact:
Experience shows no significant benefit to device operation with
auto-calibration enabled versus it disabled. To ensure consistent timing
results, Freescale recommends this feature be disabled in future customer
products. There should be no impact to parts that are already operating
in the field.
Workaround:
Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following:
1. Write a value of 0x0000_0015 to the register at offset
CCSRBAR + DDR OFFSET + 0xf30
2. Write a value of 0x2400_0000 to the register at offset
CCSRBAR + DDR OFFSET + 0xf54
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Make the fixup matchable with dts and kernel. Update the compatible from
"fsl,flexcan-v1.0" to "fsl,p1010-flexcan" and Change the "clock-freq"
property to "clock-frequency". We also change flexcan frequency from
CCB-clock to CCB-clock/2 according to P1010 spec.
We now keep the old interfaces to make previous kernel work. They should
be removed in the future.
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum A-003999: Running Floating Point instructions requires special
initialization.
Impact:
Floating point arithmetic operations may result in an incorrect value.
Workaround:
Perform a read modify write to set bit 7 to a 1 in SPR 977 before
executing any floating point arithmetic operation. This bit can be set
when setting MSR[FP], and can be cleared when clearing MSR[FP].
Alternatively, the bit can be set once at boot time, and never cleared.
There will be no performance degradation due to setting this bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
fsl_corenet_serdes.c: In function 'fsl_serdes_init':
fsl_corenet_serdes.c:511:8: warning: variable 'buf' set but not used [-Wunused-but-set-variable]
fsl_corenet_serdes.c:498:18: warning: variable 'lane_prtcl' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
tlb.c: In function 'disable_tlb':
tlb.c:175:34: warning: variable '_mas7' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
cpu_init.c: In function 'cpu_init_r':
cpu_init.c:320:7: warning: variable 'l2srbar' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Wrong pointer was being used to copy code into L2SRAM.
Also removed the unreferenced variable l2srbar.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
A few of the config registers changed definition between MMU v1.0 and
MMUv2.0. The new e6500 core from Freescale implements v2.0 of the
architecture.
Specifically, how we determine the size of TLB entries we support in the
variable size (or TLBCAM/TLB1) array is specified in a new register
(TLBnPS - TLB n Page size) instead of via TLBnCFG.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On some Freescale systems (e.g. those booted from the on-chip ROM), the
TLB that covers the boot page can also cover CCSR, which breaks the CCSR
relocation code. To fix this, we resize the boot page TLB so that it only
covers the 4KB boot page.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Verify that CCSR is actually located where it is supposed to be before
we relocate it. This is useful in detecting U-Boot configurations that
are broken (e.g. an incorrect value for CONFIG_SYS_CCSRBAR_DEFAULT).
If the current value is wrong, we enter an infinite loop, which is handy
for debuggers.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early
verion silicons. This workaround detects if the eTSEC Rx logic is properly
initialized, and reinitialize the eTSEC Rx logic.
Signed-off-by: Gong Chen <g.chen@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
U-Boot Makefiles contain a number of tests for compiler features etc.
which so far are executed again and again. On some architectures
(especially ARM) this results in a large number of calls to gcc.
This patch makes sure to run such tests only once, thus largely
reducing the number of "execve" system calls.
Example: number of "execve" system calls for building the "P2020DS"
(Power Architecture) and "qong" (ARM) boards, measured as:
-> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board>
-> grep execve /tmp/foo | wc -l
Before: After: Reduction:
==================================
P2020DS 20555 15205 -26%
qong 31692 14490 -54%
As a result, built times are significantly reduced, typically by
30...50%.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Albert Aribaud <albert.aribaud@free.fr>
cc: Graeme Russ <graeme.russ@gmail.com>
cc: Mike Frysinger <vapier@gentoo.org>
Tested-by: Graeme Russ <graeme.russ@gmail.com>
Tested-by: Matthias Weisser <weisserm@arcor.de>
Tested-by: Sanjeev Premi <premi@ti.com>
Tested-by: Simon Glass <sjg@chromium.org>
Tested-by: Macpaul Lin <macpaul@gmail.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For P3060 and P4080, USB pins are multiplexed with other functions.
Update the device tree status for USB ports based on setting of
RCW[EC1] & RCW[EC2] which describe if pins are muxed to usb.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch is intended to initialize RMan LIODN related registers on
P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to
qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Update device tree handling for SRIO controller to support updated
fsl,srio device tree binding.
We handle disabling of individual ports, the whole controller, RMU, and
RMAN. Additionally, we setup the SRIO related LIODNs in the device
tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Properly set the LIODN values associated with SRIO controller. On
P4080/P3060 we have an LIODN per port and one for the RMU. On
P2041/P3041/P5020 we have 2 LIODNs per port.
Update the tables for all of these devices to properly handle both
styles.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 'master' of git://git.denx.de/u-boot-fdt:
powerpc/85xx: use fdt_create_phandle() to create the Fman firmware phandles
fdt: update fdt_alloc_phandle to use fdt_get_phandle
fdt: check for fdt errors in fdt_create_phandle
fdt: Add a do_fixup_by_path_string() function
Function fdt_create_phandle() conveniently creates new phandle properties
using both "linux,phandle" and "phandle", so it should be used by all code
that wants to create a phandle.
The Fman firmware code, which embeds an Fman firmware into the device tree,
was creating the phandle properties manually. Instead, change it to use
fdt_create_phandle().
Signed-off-by: Timur Tabi <timur@freescale.com>
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the
P3060 and should always be set to zero.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P3041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041 has 10 qman portals, we need to configure all of them:
* As there are only 4 physical cores sdest can only be 0 to 3
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P5020 has 10 qman portals, we need to configure all of them:
* As there are only 2 physical cores sdest can only be 0 or 1
* We assign dqrr & frame data LIODNs for all portals so if they
are utilized the proper mapping tables can be setup uniquely
(PAMU stashing)
* We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN
assignments are tuned around an assumption of at most 5
partitions.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is long over due. All but two net drivers have been converted, but
those have now been dropped.
The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined. So here we scrub the
core code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Add P3060 SoC specific information:cores setup, LIODN setup, etc
The P3060 SoC combines six e500mc Power Architecture processor cores with
high-performance datapath acceleration architecture(DPAA), CoreNet fabric
infrastructure, as well as network and peripheral interfaces.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each
Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2
Rings per JQ). This just handles RAID Engine in non-DPAA mode.
Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document.
Any local bus transaction may fail during LBIU resynchronization
process when the clock divider [CLKDIV] is changing. Ensure there
is no transaction on the local bus for at least 100 microseconds
after changing clock divider LCRR[CLKDIV].
Refer to the erratum LBIU3 of mpc8548.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some
early version silicons. The default settings of the DDR IO receiver
biasing may not work at cold temperature. When a failure occurs,
a DDR input latches an incorrect value. The workaround will set the
receiver to an acceptable bias point.
Signed-off-by: Gong Chen
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
(Please note that ISBC expects all these addresses, images to be
validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
at 0xcffffffc.
Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
(The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
created by PBL/configuration word within 0 - 3.5G memory range. The
u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
PBL/configuration word after switch to AS = 1
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: Wood Scott-B07421 <B07421@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Unified DDR driver is maintained for better performance, robustness and bug
fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of
overall improvement. It requires changes for board files to customize
platform-dependent parameters.
To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx
in the header file. No more boards will be accepted without such definition.
Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1
and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8536 seems to use only 3 bits for the major revision field in the
SVR rather than the 4 bits used by all other processors. The most
significant bit is used as a mfg code on MPC8536.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration
architecture) is the ethernet contoller block. Normally it is utilized
via Queue Manager (Qman) and Buffer Manager (Bman). However for boot
usage the FMan supports a mode similar to QE or CPM ethernet collers
called Independent mode.
Additionally the FMan block supports multiple 1g and 10g interfaces as a
single entity in the system rather than each controller being managed
uniquely. This means we have to initialize all of Fman regardless of
the number of interfaces we utilize.
Different SoCs support different combinations of the number of FMan as
well as the number of 1g & 10g interfaces support per Fman.
We add support for the following SoCs:
* P1023 - 1 Fman, 2x1g
* P4080 - 2 Fman, each Fman has 4x1g and 1x10g
* P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Dai Haruki <dai.haruki@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some SOCs have discontiguously-numbered cores, and so we can't determine the
valid core numbers via the FRR register any more. We define
CPU_TYPE_ENTRY_MASK to specify a discontiguous core mask, and helper functions
to process the mask and enumerate over the set of valid cores.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The old fdt_create_phandle didn't actually create a phandle it just
set one. We'll introduce a new helper that actually does creation.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Add ifdef protection around fman specific code related to device tree
clock setup. If we dont have CONFIG_SYS_DPAA_FMAN defined we shouldn't
be executing this code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Issue: Address masking doesn't work properly.
When sum of the base address, defined by BA, and memory bank size,
defined by AM, exceeds 4GB (0xffff_ffff) then AMASKn[AM] doesn't mask
CSPRn[BA] bits.
Impact:
This will impact booting when we are reprogramming CSPR0(BA) and
AMASK0(AMASK) while executing from NOR Flash.
Workaround:
Re-programming of CSPR(BA) and AMASK is done while not executing from NOR
Flash. The code which programs the BA and AMASK is executed from L2-SRAM.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Issue:
Peripheral connected to IFC_CS3 may hamper booting from IFC.
Impact:
Boot from IFC may not be successful if IFC_CS3 is used.
Workaround:
If IFC_CS3 is used, gate IFC_CS3 while booting from NAND or NOR.
Also Software should select IFC_CS3 using PMUXCR[26:27] = 0x01.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Issue:
The NOR-FCM does not support access to unaligned addresses for 16 bit port size
Impact:
When 16 bit port size is used, accesses not aligned to 16 bit address boundary
will result in incorrect data
Workaround:
The workaround is to switch to GPCM mode for NOR Flash access.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
