Commit graph

35136 commits

Author SHA1 Message Date
Masahiro Yamada
4feefdcfe9 usb: add clock support for generic EHCI
This driver is designed in a generic manner, so clocks should be
handled genericly as well.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-25 21:50:10 +01:00
Ted Chen
9dc8ba19c5 usb: eth: add Realtek RTL8152B/RTL8153 DRIVER
This patch adds driver support for the Realtek RTL8152B/RTL8153 USB
network adapters.

Signed-off-by: Ted Chen <tedchen at realtek.com>
[swarren, fixed a few compiler warnings]
[swarren, with permission, converted license header to SPDX]
[swarren, removed printf() spew during probe()]
Signed-off-by: Stephen Warren <swarren at nvidia.com>
2016-01-23 16:22:34 +01:00
Stephen Warren
1ff6015ecb ARM: rpi: enable USB keyboard
Now that the DWC2 driver supports split transactions, we can reasonably
enable support for USB keyboards. This wasn't terribly useful before
since keyboards are usually LS/FS devices, and thus require split
transaction support when attached to a USB hub such as the hub built into
the RPi model Bs.

Cc: Stefan Brüns <stefan.bruens@rwth-aachen.de>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2016-01-23 16:21:55 +01:00
Stefan Brüns
25612f23b5 usb: dwc2: Do not mix data toggle for IN and OUT endpoints, check bounds
USB protocol allows for 16 IN and 16 OUT endpoints (USB 2.0 Spec,
8.3.2.2 Endpoint Field). A function may have an EP 1 for both IN and OUT,
so these two should be kept separate. As EPs are either BULK or INTERRUPT
(or ISO), it is fine to have one array per direction for all transfer
types (also see e236519b73).

USB device address is 7 bits, so a bus may have more than 16 devices.
Check the device number, as the DWC2 driver only supports BULK/ISO for
the first 16 devices.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2016-01-23 16:21:11 +01:00
Stefan Brüns
d2ff51b372 usb: dwc2: Add SPLIT INTERRUPT transaction support
CSPLITs for INTERRUPT transactions have to be scheduled in each microframe
following the SSPLIT. INTERRUPT transfers are executed in the next even/
odd microframe depending on the HCCHAR_ODDFRM flag.

As there are no handshakes for INTERRUPT SSPLITs the SSPLIT may have
failed (transport error) without the error being detected by the host
driver. If the last CSPLIT is not received within 4 microframes after the
SSPLIT there was a transaction error and the complete transaction has
to be restarted.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2016-01-23 16:21:11 +01:00
Stefan Brüns
b54e447052 usb: dwc2: Implement SPLIT transaction support
In contrast to non-SPLIT transfers each transaction has to be submitted
as an individual chunk.
The transaction state machine proceeds from SSPLIT to CSPLIT if the ACK
flag is set. CSPLIT has to be repeated while NYET is set.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2016-01-23 16:21:11 +01:00
Stefan Brüns
890f0ee4bb usb: dwc2: add helper function for setting SPLIT HC registers
The split register setting is used for both SSPLIT and CSPLIT transactions,
the bit for CSPLIT has to be set seperately.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2016-01-23 16:21:11 +01:00
Stefan Brüns
daed305941 usb: dwc2: split transfer core from outer loop
Split the movement of data between CPU and Host Controller from the
status handling and tracking of transfer progress.
This will also simplify adding of SPLIT transaction support.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2016-01-23 16:21:11 +01:00
Stefan Brüns
03460cdc3d usb: dwc2: Simplify wait_for_chhltd(), remove ignore_ack
A transfer is completed if the XFERCOMP flag is set, irrespective of the
ACK flag. BULK OUT transfers to some HS devices complete without having
the ACK flag set, which signal the devices has responded with an NYET
to the transfer (PING protocol).
The new behaviour matches the Linux kernel minus any PING protocol.

Also see 5966defabdcc (usb: dwc2: fix bulk transfers)

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2016-01-23 16:21:11 +01:00
Stefan Brüns
56a7bbd741 usb: dwc2: Fix out-of-bounds access, fix chunk size
Fix two errors in transfer len calculation, move loop invariant code out
of loop.

If xfer_len is equal to CONFIG_DWC2_MAX_TRANSFER_SIZE (or slightly
smaller), the xfer_len will be to large, e.g.:
  xfer_len = MAX_TRANSFER_SIZE = 65535
  max packet size = 512
    => num_packets = 128
    => IN xfer_len = 65536

For OUT transactions larger than (65536 - mps) bytes, the xfer_len
determination is quite awkward, it is only correct due to:
- max_packet_size for control/bulk/interrupt is required to be
  power-of-two.
- (CONFIG_DWC2_MAX_TRANSFER_SIZE + 1) % max-packet-size is zero
  for all allowed (2^3 ... 2^9) packet sizes

As the max xfer len is loop invariant, it can be moved out of the loop.

Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de>
2016-01-23 16:21:10 +01:00
Tom Rini
12f229ea8f Merge git://git.denx.de/u-boot-fdt 2016-01-22 17:01:22 -05:00
Thomas Chou
67871a5958 devicetree: use wildcard to clean arch subdir
Use wildcard to clean arch subdirectories, as it is cleaner than
listing all the arch which builds dtb.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-22 14:41:14 -07:00
Simon Glass
f138713073 rockchip: Update the README
GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC.
There is an implementation to run the CPU at full speed although it does
not seem to make much difference.

Update the README to cover recent developments.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
7c1058fadc rockchip: Add support for Raxda Rock 2
This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.

So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.

Thanks to Tom Cubie for sending me a board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
cf629bb2ba rockchip: rock2: dts: Make changes for U-Boot
Add the required pre-relocation tags and SDRAM init information for U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
68b08c4077 rockchip: rock2: Bring in device tree files from Linux
Bring in the current device tree files for rock2 from linux/next commit
719d6c1. Hopefully this is the latest one.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
6406f45354 rockchip: dts: Sync up SPDIF node with Linux
This has been added and we have references to it in the rock2 board. Add
this node.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
889b8a3147 rockchip: firefly-rk3288: Enable HDMI output
Enable HDMI output and a console on firefly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
74336f7daa rockchip: jerry: Enable EDP and HDMI video output
Enable these devices using the VOPL video output device. We explicitly
disable VOPB in the device tree to avoid it taking over. Since this device
has an LCD display this comes up by default. If the display fails for some
reason then it will attempt to use HDMI. It is possible to force it to fail
(and thus fall back to HDMI) by puting 'return -EPERM' at the top of
rk_edp_probe(). For now there is no easy way to select between the two.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
d78a3d2045 rockchip: jerry: Add support for timing SPI flash speed
Add the 'time' and 'sf test' commands so that we can test SPI flash
performance.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
dae594f210 rockchip: spl: Support full-speed CPU in SPL
Add a feature which speeds up the CPU to full speed in SPL to minimise
boot time. This is only supported for certain boards (at present only
jerry).

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
318922b30f rockchip: rk3288: pinctrl: Fix HDMI pinctrl
Since the device tree does not specify the EDID pinctrl option for HDMI we
must set it manually. Fix the driver to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
c87c129f7f rockchip: rk3288: clock: Fix various minor errors
Fix a number of small errors which were found in reviewing the clock code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
4f14d135f9 rockchip: jerry: Fix the SDRAM timing
There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
f23cf909ee rockchip: spl: Drop MMC support code when not needed
When the board does not use MMC SPL this code is a waste of space. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
affd4a9fa0 rockchip: Tidy up the register-access macros
These work reasonable well, but there are a few errors:

- Brackets should be used to avoid unexpected side-effects
- When setting bits, the corresponding upper 16 bits should be set also

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
2460d18c33 rockchip: sdram: Use syscon_get_first_range() where possible
This is a shortcut to obtaining a register address. Use it where possible, to
simplify the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
9368104d2f rockchip: sdram: Tidy up a few comments
Fix spaces in two comments in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
30fc0fdded rockchip: config: Enable the 'gpio' command
Now that we have a pretty good GPIO driver, enable the 'gpio' command on all
rockchip boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
002c634c1f rockchip: Add a script to parse datasheets
This script has proved useful for parsing datasheets and creating register
shift/mask values for use in header files. Include it in case it is useful
for others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
74e53e0e9b rockchip: Add a simple 'clock' command
Add a command that displays the PLLs and their current rate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
ad443b7290 rockchip: Don't skip low-level init
At present the low-level init is skipped on rockchip. Among other things
this means that the instruction cache is left disabled. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
7b7ad5c31c rockchip: video: Add a video-output driver
Some rockchip SoCs include video output (VOP). Add a driver to support this.
It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and
eDP are supported.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
5852d539ea rockchip: video: Add a display driver for rockchip eDP
Some Rockchip SoCs support embedded DisplayPort output. Add a display driver
for this so that these displays can be used on supported boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
c253948341 rockchip: video: Add a display driver for rockchip HDMI
Some Rockchip SoCs support HDMI output. Add a display driver for this so
that these displays can be used on supported boards.

Unfortunately this driver is not fully functional. It cannot reliably read
EDID information over HDMI. This seems to be due to the clocks being
incorrect - the I2C bus speed appears to be up to 100x slower than the
clock settings indicate. The root cause may be in the clock logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
830a608170 rockchip: clk: Add support for clocks needed by the displays
The displays need to use NPLL and also select some new peripheral clocks.
Add support for these to the clock driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
009741fbae rockchip: Rename the CRU_MODE_CON fields
These should match the datasheet naming. Adjust them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
2dcf143398 dm: video: Repurpose the 'displayport' uclass to 'display'
The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.

Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.

Also update nyan-big which is affected by this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
cd9c2070ea video: panel: Add a simple panel driver
Most panels are very simple - they just have a power supply and a backlight.
Add a driver which supports this and implements the enable_backlight()
method.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
f563dc1d19 dm: panel: Add a panel uclass
LCD panels can usefully be modelled as their own uclass. They can be probed
(which powers them up ready for use). If they have a backlight, this can be
enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
65fba5927c dm: backlight: Add a driver for a PWM backlight
Many backlights need to use a PWM to control the brightness. Add a driver
for this. It understands the standard device tree binding.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
363bf77acc dm: backlight: Add a backlight uclass
LCD panels normally have a backlight which can be controlled to illuminate
the LCD contents. Add a uclass to support this. Initially it only has a
method to enable the backlight.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
0e23fd81a5 pwm: rockchip: Add a PWM driver for Rockchip SoCs
Add a simple driver which implements the standard PWM uclass interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
fc760cb8c4 dm: pwm: Add a PWM uclass
Add a uclass that supports Pulse Width Modulation (PWM) devices. It
provides methods to enable/disable and configure the device.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
d4bf91ada1 video: bridge: Allow GPIOs to be optional
Some video bridges will not have GPIOs to control reset, etc. Allow these
to be optional.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
68dcdc99c5 video: Add a function to control cache flushing
Allow the cache-flushing function of a video device to be controlled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
f1a1247d89 video: Name consoles by their number
We must use the console name in the 'stdout' variable to select the one
we want. At present the name is formed from the driver name with a suffix
indicating the rotation value.

It seems better to name them sequentially since this can be controlled by
driver order. So adjust the code to use 'vidconsole' for the first,
'vidconsole1' for the second, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
66280e82f7 gpio: Warn about invalid GPIOs used with the 'gpio' command
At present there is no indication that an invalid GPIO is used except that
the GPIO status is not displayed. Make the error more explicit to avoid
confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
35a1f0dfa1 stdio: Correct a build error with driver model
When driver model is used for video but not for the keyboard, a compiler
warnings is produced. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00
Simon Glass
27a1961d0b rockchip: jerry: Enable the Chrome OS EC
Turn on the EC and enable the keyboard.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:36 -07:00