Commit 1eb0c03c21 added
SPL_SYS_MALLOC_SIMPLE Kconfig option and changed the way it is
evaluated.
Thus, the definitions of CONFIG_SYS_MALLOC_SIMPLE in rk3***_common.h
board configs are now incorrect because CONFIG_SPL_BUILD is enabled so
CONFIG_IS_ENABLED(SYS_MALLOC_SIMPLE) will look for SPL_SYS_MALLOC_SIMPLE
instead of SYS_MALLOC_SIMPLE.
This commit fix this enabling SPL_SYS_MALLOC_SIMPLE with the new Kconfig
option by default in rockchip-mach.
Signed-off-by: Ariel D'Alessandro <ariel@vanguardiasur.com.ar>
Acked-by: Simon Glass <sjg@chromium.org>
This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Moved board Kconfig fragment from previous patch into this one to fix
build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- moved board Kconfig fragment from previous patch into this one
rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
some soc(rk3036 etc) use dw_mmc but do not have internal dma,
so we implement fifo mode to read and write data.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
some rockchips soc will not use uclass in SPL stage,
so define config to decide whether to build common.c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
some rockchip soc will not include lib/timer.c in SPL stage,
so implement timer driver for some soc can use us delay function in SPL.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Save the environment on the SD card for Firefly in the empty space
between the SPL and the u-boot image.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Similar to load an fdt, when loading an initrd about the 512Mb mark
things seem to break. For now force loading below 512Mb until the reason
why this fails has been determined/solved.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
We eventually need to drop the compatibility functions for driver model. As
a first step, create a configuration option to enable them and hide them
when the option is disabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust this command to use the correct PCI functions, instead of the
compatibility layer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
With driver mode, struct pci_controller is stored as uclass-private data.
Add a comment to that effect.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust the Tegra PCI driver to support driver model and move all boards over
at the same time. This can make use of some generic driver model code, such
as the range-decoding logic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
This function looks up the controller and returns a pointer to each region
type.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
A PCI bus may be a bridge device where the controller is the bridge's
parent. Add a function to return the controller device, given a PCI device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Provide a few functions to support using 32-bit access to emulate 8- and
16-bit access.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
This is not supported with driver model, so print a message instead of
generating a build error. Rescanning PCI is not yet implemented.
This function will be implemented later once some additional PCI driver
model improvements are merged. It was confirmed on the mailing list
that no one on the tegra side will miss this feature, so it is disabled
for tegra.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
To group all dm timer drivers together, move tsc timer to
drivers/timer directory.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
There are timers with a 64-bit counter value but current timer
uclass driver assumes a 32-bit one. Modify timer_get_count()
to ask timer driver to always return a 64-bit counter value,
and provide an inline helper function timer_conv_64() to handle
the 32-bit/64-bit conversion automatically.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This changes 'Timer' to 'timer' at several places.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
As the environment variables "serial#" and "ethaddr" need to be
overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable
the write protection. Anybody can change or delete these parameters.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.
To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0xffffffff too.
This patch is to update fdt_high and initrd_high for LS1021AQDS board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.
Signed-off-by: York Sun <yorksun@freescale.com>
Add support for the third USB controller for LS1043A.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Use the U-Boot Driver Model. Just enable Freescale DSPI driver
and set DSPI related parameters in dts file.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
As per current implementation of DPAA2 ethernet driver DPNI is used as
net device. DPNI is tangible objects can be multiple connected to same physical lane.
Use DPMAC as net device where it represents physical lane.
Below modification done in driver
- Use global DPNI object
- Connect DPMAC to DPNI
- Create and destroy DPMAC
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.
Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.
Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DPMAC represents physical line on the board. This physical
line eventually asscociate with on-board PHY.
So Add an api to return linked PHY ID of DPMAC object.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DPMAC object of Management complex controls Physical MAC and MDIO controller.
It provides APIs for MDIO and link state updates. It also provides APIs for
PHY/link configuration.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Current Management Complex Flibs does not support APIs for adding and
destroying the objects.
Add APIs to create and destroy objects for DPBP, DPIO, DPNI and DPRC.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Remove fsloadcmd / ext2load as we are using load command
which use the corresponding latest file system command.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
socfpga_dw_mmc driver will obtain the drvsel and
smplsel value from device tree instead of definition
in config header file.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Marek Vasut <marex@denx.de>
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
When adding support for the Arria10 platform, we're going to name the file
base_addr_a10.h, so to be systematic about it, rename the socfpga_base_addr.h
to be base_addr_ac5.h for the Arria5 and Cyclone5 platform.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Give default CONFIG_SYS_MAX_FLASH_SECT in flash.h, so that
the header can be included regardless of the present of flash.
The value 512 is the most used.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch add ZyXEL NSA310S 1-Bay Media Server
The ZyXEL NSA310S device is a Kirkwood based NAS:
- SoC: Marvell 88F6702 1000Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 4 Status LED (green)
- 1 Copy/Sync button
- 1 Reset button
- 1 SATA II port
- 2 USB 2.0 ports (front and back)
- Smart fan
Signed-off-by: Gerald Kerma <dreagle@doukki.net>
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Luka Perkov <luka.perkov@sartura.hr>
Use the correct function name in the function description.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
There are already Kconfig options for SPI flash drivers, but we
have not moved them from config.h to defconfig files. This commit
does this in a batch.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
There are already Kconfig options for SPI drivers, but we
have not moved them from config.h to defconfig files. This
commit does this in a batch.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Congatec has several MX6 boards based on quad, dual, dual-lite and solo.
Add SPL support so that all the variants can be supported
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Congatec boards boot from SPI NOR, so it makes more sense to use
SPI NOR to store the environment variables.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit provides definition and declaration of GPT verification
functions - namely gpt_verify_headers() and gpt_verify_partitions().
The former is used to only check CRC32 of GPT's header and PTEs.
The latter examines each partition entry and compare attributes such as:
name, start offset and size with ones provided at '$partitions' env
variable.
Signed-off-by: Lukasz Majewski <l.majewski@majess.pl>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Using 50 MiB malloc pool in SPL is nonsense. Since the caches are not
enabled in SPL, it takes 2 seconds to init the pool and has no obvious
benefit. Reduce the size to 1 MiB.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Add initial sun8i H3 support, only uart + mmc are supported for now.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The DFU protocol implementation in U-Boot is much faster than the
FEL protocol implementation in the boot ROM on Allwinner devices.
Using DFU instead of FEL improves the USB transfer speed from
500-900 KB/s to 3.2-3.7 MB/s. This is particularly useful for
reducing the time needed for booting systems with large initrd
images.
FEL is still useful for loading the U-Boot bootloader and a boot
script, which may then activate DFU in the following way:
setenv dfu_alt_info ${dfu_alt_info_ram}
dfu 0 ram 0
bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
The rest of the files can be transferred to the device using the
"dfu-util" tool.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add support for storing the environment in CFI NOR flash on Juno and FVP
models.
I also removed some config values that are not used by CFI flash parts.
Juno has 1 flash part with 259 sectors. The first 255 sectors are
0x40000 (256kb) and are followed by 4 sectors of 0x10000 (64KB).
FVP models simulate a 64MB NOR flash part at base address 0x0FFC0000.
This part has 256 x 256kb sectors. We use the last sector to store the
environment.
To save the NOR flash to a file, the following parameters should be
passed to the model:
-C bp.flashloader1.fname=${FILENAME}
-C bp.flashloader1.fnameWrite=${FILENAME}
Foundation models don't simulate the NOR flash, but having NOR support
in the u-boot binary does not harm: attempting to write to the NOR will
fail gracefully.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This patch allows vexpress64 targets to be compiled when
CONFIG_SYS_FLASH_CFI is enabled.
I considered using #warning instead of #error, but this just clutters up
the build output and hides real warnings.
Without this patch, you see errors during compilation like this:
include/configs/vexpress_aemv8a.h:42:2: error: #error "Unknown board
variant"
#error "Unknown board variant"
include/configs/vexpress_aemv8a.h:115:2: error: #error "Unknown board
variant"
#error "Unknown board variant"
include/configs/vexpress_aemv8a.h:280:2: error: #error "Unknown board
variant"
#error "Unknown board variant"
make[1]: *** [tools/envcrc.o] Error 1
make: *** [tools] Error 2
In file included from include/config.h:5:0,
from tools/envcrc.c:19:
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
This patch makes the 2nd DRAM bank available on Juno only and not on
other vexpress64 targets, eg. the FVP models.
The commit below added a 2nd bank of NOR flash for Juno, but also for
all vexpress64 targets:
commit 2d0cee1ca2
Author: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Date: Mon Oct 19 11:08:31 2015 +0100
vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Unfortunately, I only fully tested on Juno R0, R1 and the FVP Foundation
model. Whilst FVP Base AEMV8 models run U-Boot OK, they fail to boot
the kernel.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Add bus argument to eeprom_init(), so that it can select
the I2C bus number on which the eeprom resides. Any negative
value of the $bus argument will preserve the old behavior.
This is in place so that old code does not randomly break.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
[trini: Wrap i2c_set_bus_num() call with CONFIG_SYS_I2C test]
Signed-off-by: Tom Rini <trini@konsulko.com>
Remove this function as it's no longer used.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
This option only complicates the code unnecessarily, just use
CONFIG_SYS_DEF_EEPROM_ADDR as the default address if there are
only five arguments to eeprom {read/write} if this is defined.
If CONFIG_SYS_DEF_EEPROM_ADDR is not defined, we mandate all
six arguments.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
The NOR flash on Keystone 2 evms has a u-boot-spl partition size of
0x80000.
Currently burn_uboot_spi will erase 0x100000 from the spi NOR which will
cause a partial erase of the misc partition.
Fix this by correcting the erase size.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Change to ns16550 uart for 10m50 devboard based on a new
Altera release.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Zap CONFIG_NS16550_SERIAL, as the unification of ns16550 drivers
is completed.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Unify serial_omap, and use the generic binding.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Unify serial_tegra, and use the generic binding.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Unify serial_dw, and use the generic binding.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Unify serial_keystone, and use the generic binding.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
Add a simple USB keyboard driver for sandbox. It provides a function to
'load' it with input data, which it will then stream through to the normal
U-Boot input subsystem. When the input data is exhausted, the keyboard stops
providing data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Each USB device has an emulator. Currently this can only be found by
supplying the 'pipe' value, which contains the device number. Add a way
to find it directly from the emulated device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Allow console recording so that tests can use it. Also allow the console
output to be suppressed, to reduce test output 'noise'.
Signed-off-by: Simon Glass <sjg@chromium.org>
It is useful to be able to record console output and provide console input
via a buffer. This provides sandbox with the ability to run a command and
check its output. If the console is set to silent then no visible output
is generated.
This also provides a means to fix the problem where tests produce unwanted
output, such as errors or warnings. This can be confusing. We can instead
set the console to silent and record this output. It can be checked later
in the test if required.
It is possible that this may prove useful for non-test situations. For
example the console output may be suppressed for normal operations, but
recorded and stored for access by the OS. That feature is not implemented
at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
This will be used to support console recording. It provides for a circular
buffer which can be written at the head and read from the tail. It supports
avoiding data copying by providing raw access to the data.
Signed-off-by: Simon Glass <sjg@chromium.org>
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
When sending LED update command to an i8042 compatible keyboard,
bit1 is 'Num Lock' and bit2 is 'Caps Lock' in the data byte. But
input library defines bit1 as 'Caps Lock' and bit2 as 'Num Lock'.
This causes a wrong LED to be set on an i8042 compatible keyboard.
Change the LED state bits to be i8042 compatible, and change the
keyboard flags as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This has duplicated scan code tables and logic. We can use the input
library to implement most of the features here.
This needs testing. The only supported board appears to be TQM5200.
Unfortunately no maintainer is listed for this board.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust this driver to support driver model. The only users are x86 boards
so this should be safe.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Some boards have an i8042 device. Enable the driver for all x86 boards, and
add a device tree node for those which may have this keyboard.
Also adjust the configuration so that i8042 is always separate from the VGA,
and rename the stdin driver accordingly. With this commit the keyboard will
not work, but it is fixed in the next commit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function which returns a new keyboard LED value when the LEDs need
updating.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add support for the German keymap, taken from i8042.c. This can be selected
when the input library it initialised.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a sandbox timer which get time from host os and a basic
test.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Generally the input library handles processing of a list of scanned keys.
Repeated keys need to be generated based on a timer in this case, since all
that is provided is a list of keys current depressed.
Keyboards which do their own scanning will resend codes when they want to
inject a repeating key. Provide a function which tells the input library to
accept repeating keys and not to try to second-guess the caller.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Most keyboards can be scanned to produce a list of the keycodes which are
depressed. With the i8042 keyboard this scanning is done internally and
only the processed results are returned.
In this case, when a key is pressed, a 'make' code is sent. When the key
is released a 'break' code is sent. This means that the driver needs to
keep track of which keys are pressed. It also means that any protocol error
can lead to stuck keys.
In order to support this type of keyboard, add a function when can be used
to provide a single keycode and either add it to the list of what is pressed
or remove it from the list. Then the normal input_send_keycodes() function
can be used to actually do the decoding work.
Add debugging to display the ASCII characters written to the input queue
also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
CONFIG_CONSOLE_CURSOR, CONFIG_SYS_CONSOLE_BLINK_COUNT and
CONFIG_CONSOLE_TIME are not used by any board. The implementation is not
great and stands in the way of a refactor of i8042. Drop these for now.
They can be re-introduced quite easily later, perhaps with driver-model
real-time-clock (RTC) support.
When reintroducing, it might be useful to make a few changes:
- Blink time would be more useful than blink count
- The confusing #ifdefs should be avoided
- The time functions should support driver model
- It would be best keyed off console_tstc() or some similar idle loop
rather than a particular input driver (i8042 in this case)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust the tegra keyboard driver to support driver model, using the new
uclass. Make this the default for all Tegra boards so that those that use
a keyboard will build correctly with this driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
In preparation for converting the cros_ec keyboard driver to driver model,
adjust the cros_ec functions it will use to use a normal struct udevice.
Signed-off-by: Simon Glass <sjg@chromium.org>
