Commit graph

10574 commits

Author SHA1 Message Date
Stefano Babic
4f66e09bb9 Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
2017-05-09 18:03:44 +02:00
Maxim Sloyko
78df5e1ed0 dm: Update Simple Watchdog uclass
- Remove "probe" function from sandbox wdt driver
- Fix include order

Fixes: 0753bc2d30 ("dm: Simple Watchdog uclass")
Signed-off-by: Maxim Sloyko <maxims@google.com>
[trini: Create as the delta between v1 (applied) and v2 (should have
 applied)].
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-09 09:08:07 -04:00
Tom Rini
a6d4cd4778 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-05-08 15:44:44 -04:00
maxims@google.com
defb184904 aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:35 -04:00
maxims@google.com
3b95902d47 aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.

The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.

The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.

So, the network driver would only need to enable these clocks, no need
to configure the rate.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:35 -04:00
maxims@google.com
4dc038f3a1 aspeed: Add I2C Driver
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
2017-05-08 11:57:34 -04:00
maxims@google.com
4999bb06cc aspeed: Add P-Bus clock in ast2500 clock driver
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:34 -04:00
maxims@google.com
4f0e44e466 aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.

Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:33 -04:00
maxims@google.com
99f8ad7321 aspeed: Refactor AST2500 RAM Driver and Sysreset Driver
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.

To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.

Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.

These were the only users of the old Watchdog API, so that API is
removed.

This all is done in one change to avoid having to maintain dual API for
watchdog in between.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:32 -04:00
maxims@google.com
858d497629 aspeed: Reset Driver
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:

rst: reset-controller {
    compatible = "aspeed,ast2500-reset";
    aspeed,wdt = <&wdt1>;
}

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:32 -04:00
maxims@google.com
413353b30b aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:31 -04:00
maxims@google.com
1eb0a464b7 aspeed: Watchdog Timer Driver
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:31 -04:00
maxims@google.com
0753bc2d30 dm: Simple Watchdog uclass
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:30 -04:00
Chris Packham
d425d6056e rtc: Add DM support to ds1307
Add an implementation of the ds1307 driver that uses the driver model
i2c APIs.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:28 -04:00
Ladislav Michl
18cae43b62 mtd: nand: Consolidate nand spl loaders implementation
nand_spl_load_image implementation was copied over into three
different drivers and now with nand_spl_read_block used for
ubispl situation gets even worse. For now use least intrusive
solution and #include the same implementation to nand drivers.

Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-05-08 11:57:26 -04:00
Vikas Manocha
58fb3c8d89 stm32f7: increase the max no of pin configuration to 70
The number of pins to be configured could be more than 50 e.g. in case
of sdram controller, there are about 56 pins (32 data lines, 12 address
& some control signals).

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:23 -04:00
Vikas Manocha
bfea69ad27 stm32f7: sdram: correct sdram configuration as per micron sdram
Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.

Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to cycles.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:22 -04:00
Vikas Manocha
57af3cc32a stm32f7: stm32f746-disco: read memory info from device tree
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:57:21 -04:00
Vikas Manocha
280057bd7d stm32f7: use stm32f7 gpio driver supporting driver model
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.

Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-08 11:57:21 -04:00
Vikas Manocha
774171020b dm: gpio: Add driver for stm32f7 gpio controller
This patch adds gpio driver supporting driver model for stm32f7 gpio.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christophe KERELLO <christophe.kerello@st.com>
[trini: Add depends on STM32]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-08 11:57:02 -04:00
Vikas Manocha
6c9a10034a stm32f7: sdram: use sdram device tree node to configure sdram controller
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:05 -04:00
Vikas Manocha
d0b24c1aa9 stm32f7: use clock driver to enable sdram controller clock
This patch also removes the sdram/fmc clock enable from board specific
code.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:04 -04:00
Vikas Manocha
910a52ede3 stm32f7: dm: add driver model support for sdram
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:02 -04:00
Vikas Manocha
bf1ae4426b stm32f7: sdram: move sdram driver code to ram drivers area
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:39:02 -04:00
Vikas Manocha
890bafd752 stm32f7: use clock driver to enable qspi controller clock
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:38:41 -04:00
Uri Mashiach
4acfe1ae46 arm: am57xx: cl-som-am57x: invoke clock API to enable/disable clocks
Invoke enable_usb_clocks during board_usb_init and disable_usb_clocks
during board_usb_exit to enable and disable clocks respectively.

Modifications:
* Enable USB clocks in the OMAP version of the function
  board_usb_init.
* Disable USB clocks in the OMAP version of the function
  board_usb_cleanup.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 11:38:38 -04:00
Uri Mashiach
1a9a5f7a39 usb: host: xhci-omap: fix double weak board_usb_init functions
A weak version of the function board_usb_init is implemented in:
common/usb.c
drivers/usb/host/xhci-omap.c

To fix the double implementations:
* Convert the board_usb_init function in drivers/usb/host/xhci-omap.c
  normal (not weak).
* The function board_usb_init in drivers/usb/host/xhci-omap.c calls to
  the weak function omap_xhci_board_usb_init.
* Rename board version of the function board_usb_init to
  omap_xhci_board_usb_init.
  Done only for boards that defines CONFIG_USB_XHCI_OMAP.

To achieve the same flexibility with the function board_usb_cleanup:
* Add a normal (not weak) implementation of the function
  board_usb_cleanup in drivers/usb/host/xhci-omap.c
* The function board_usb_cleanup in drivers/usb/host/xhci-omap.c calls
  to the weak function omap_xhci_board_usb_cleanup.
* Rename board version of the function board_usb_cleanup to
  omap_xhci_board_usb_cleanup.
  Done only for boards that defines CONFIG_USB_XHCI_OMAP.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
2017-05-08 11:38:37 -04:00
Uri Mashiach
ef3f3b8100 arm: usb: dra7xx: xHCI registers based on USB port index
Modify the determination of the base address of xHCI registers of DRA7XX
targets.
Before the commit: by the target.
After the commit: by the USB port index.

Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Roger Quadros <rogerq@ti.com>
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2017-05-08 11:38:36 -04:00
Suniel Mahesh
2f54205829 drivers: spi: Remove duplicate .probe method
.probe method has been assigned twice when declaring
a driver with U_BOOT_DRIVER(). Removed one of them.
Here is the last commit which had the duplicate entry:
"spi: omap3: Convert to driver model"
(sha1: 77b8d04854)

Signed-off-by: Suniel Mahesh <suniel.spartan@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03 11:52:16 +05:30
Moritz Fischer
ac6991fb5f zynq: spi: Honour the activation / deactivation delay
This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03 11:03:04 +05:30
Wenyou Yang
61a77ce1d5 spi: atmel: check GPIO validity before using cs_gpios
Before using the cs_gpio, check if the GPIO is valid or not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03 10:58:54 +05:30
Simon Glass
ae189ba1ac Drop the pdsp188x driver
This is not used in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30 13:41:02 -04:00
Simon Glass
983b103f1c Convert CONFIG_SYS_WHITE_ON_BLACK to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_WHITE_ON_BLACK

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Make this default y on various SoCs]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-30 13:40:13 -04:00
Simon Glass
bdf25a5e04 power: Convert CONFIG_PMIC_AS3722 to Kconfig
This converts the following to Kconfig:
   CONFIG_PMIC_AS3722

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30 10:29:50 -04:00
Simon Glass
2838c07f47 power: Move as3722 pmic to pmic/ directory
Most of the PMICs are in the drivers/power/pmic/ directory. Move this one
there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30 10:29:49 -04:00
Simon Glass
56aceaf282 power: Rename CONFIG_AS3722_POWER to CONFIG_PMIC_AS3722
Before converting this to Kconfig, rename it to match the other PMICs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-30 10:29:47 -04:00
Jernej Skrabec
56009451d8 sunxi: video: Add A64/H3/H5 HDMI driver
This commit adds support for HDMI output.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-28 09:21:25 +02:00
Jernej Skrabec
a8f01ccff2 sunxi: i2c: Add support for DM I2C
This commit adds support for DM I2C on sunxi platform. It can coexist
with old style sunxi I2C driver, because it is still used in SPL and
by some SoCs.

Because sunxi platform doesn't yet support DM clk, reset and pinctrl
driver, workaround is needed to enable clocks and set resets and
pinctrls. This is done by calling i2c_init_board() in board_init().
This means that CONFIG_I2Cx_ENABLE options needs to be correctly set
in order to use needed I2C controller.

Commit is based on the previous patch made by Philipp Tomsich

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-28 09:19:03 +02:00
Jernej Skrabec
ae4e4dde52 sunxi: power: Compile sy8106a driver only during SPL build
Driver for that regulator is used only in SPL and it uses old I2C
interface. If we want to use DM I2C in U-Boot proper, compilation of
this driver has to be limited only to SPL.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-28 09:18:54 +02:00
Philipp Tomsich
51c7f34809 pinctrl: Kconfig: sort pinctrl config options to prevent future clutter
This originally started out as
     "pinctrl: Kconfig: reorder to keep Rockchip options together"
and tried to keep the Rockchip-related config options together.

However, we now rewrite all chip-specific driver selections to start
with CONFIG_PINCTRL_ (with the inadvertent changes to related
Makefiles) and sort those alphabetically. And as this already means
touching most of the file, we also reformat the help text to not exceed
80 characters (but make full use of those 80 characters).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-27 16:49:04 -04:00
Simon Glass
43b41566f7 dm: sandbox: pwm: Add a basic pwm test
Unfortunately a test for the PWM uclass was not included when it was
submitted. This was noticed when trying to add more functionality:

   http://patchwork.ozlabs.org/patch/748172/

Add a simple test to get us started.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-27 16:49:02 -04:00
Tom Rini
6f008a2e16 Merge git://git.denx.de/u-boot-sunxi 2017-04-25 16:12:42 -04:00
Alexey Brodkin
83cb46c286 ehci-ppc4xx: Prepare for usage of readl()/writel() accessors
We used to have opencoded ehci_readl()/writel() which required no
external functions to be called.

Now with attempt to switch to generic readl()/writel() accessors
we see a missing declaration of those accessors in ehci-ppc4xx.
Something like that happens if applied
http://patchwork.ozlabs.org/patch/726714/:
---------------->8---------------
  CC      drivers/usb/host/ehci-ppc4xx.o
drivers/usb/host/ehci-ppc4xx.c: In function 'ehci_hcd_init':
drivers/usb/host/ehci-ppc4xx.c:23:3: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration]
   HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
   ^
---------------->8---------------

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-04-25 12:50:13 +02:00
Heinrich Schuchardt
7f2e59aee5 usb: musb: avoid out of bound access in udc_setup_ep
For id = 15 an out of bound access occurs in udc_setup_ep().
Increase the size of epinfo[] from 30 to 32 to encompass
ids 0..15.

The problem was highlighted by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-04-25 12:50:12 +02:00
Heinrich Schuchardt
2511b2ed4d musb: properly detect failed initialization of controller
We want to check the result of musb_init_controller
and not the address were the result is stored.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-04-25 12:50:11 +02:00
Icenowy Zheng
e8f86a0261 sunxi: fix the default value of CONS_INDEX on non-A23/A33 SUN8I
Only A23/A33 in SUN8I want a default value of CONS_INDEX of 5, for other
chips the default value is 1 like other Allwinner SoCs.

Fix this default value.

The original wrong value has lead to wrong console on H3 Orange Pi
boards.

Fixes: 7095f86418 ("sunxi: Convert CONS_INDEX to Kconfig")

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-25 11:44:21 +02:00
Jernej Skrabec
1ae5def6be sunxi: Add clock support for DE2/HDMI/TCON on newer SoCs
This is needed for HDMI, which will be added later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:37:31 +02:00
Jernej Skrabec
30ca20234e sunxi: video: Convert lcdc to use struct display_timing
Video driver for older Allwinner SoCs uses cfb console framework which
in turn uses struct ctfb_res_modes to hold timing informations. However,
DM video framework uses different structure - struct display_timing.

It makes more sense to convert lcdc to use new timing structure because
all new drivers should use DM video framework and older drivers might be
rewritten to use new framework too.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:34:52 +02:00
Jernej Skrabec
5e023e7eb3 sunxi: video: Split out TCON code
TCON unit has similar layout and functionality also on newer SoCs. This
commit splits out TCON code for easier reuse later.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:34:50 +02:00
Chen-Yu Tsai
33559ffe5b gpio: sunxi: Add compatible string for R40 PIO
The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00