Commit graph

280 commits

Author SHA1 Message Date
Simon Glass
5ba534d247 arm: Switch 32-bit ARM to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24 13:50:36 -04:00
Simon Glass
931bec31b4 arm: Switch aarch64 to using generic global_data setup
There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Tested on LS2085ARDB and LS2085AQDS (armv8 SoC).
Tested-by: York Sun <yorksun@freescale.com>

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-10-24 13:50:36 -04:00
Thierry Reding
b1964c72bd armv8/gic: Fix GIC v2 initialization
Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-15 14:47:03 +02:00
Albert ARIBAUD
13a3972585 Merge remote-tracking branch 'u-boot/master' 2015-10-14 10:46:36 +02:00
Simon Glass
1090a56c87 arm: Drop old non-generic-board code
This code is no-longer used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@gmail.com>
2015-09-28 10:48:24 -04:00
Simon Glass
ed64190f67 arm: Correct comments in crt0.S for the recent SPL improvements
The current comments need a bit of tweaking since we now support stack
and global_data relocation in SPL. Also add a reference to the README.

For AArch64 this is not implemented, so leave a TODO for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tim Harvey <tharvey@gateworks.com>
2015-09-12 09:00:35 +02:00
Tom Rini
c9feb427ab Merge git://git.denx.de/u-boot-rockchip 2015-09-03 14:57:09 -04:00
Simon Glass
c6aabe9289 arm: reset: Avoid a build error when the reset uclass is enabled
There can be only one do_reset(). When CONFIG_RESET is enabled this is
provided by the reset uclass, and ARM's version should be disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-09-02 21:28:23 -06:00
Bhupesh Sharma
3ffa95c283 armv8: Add framework for CCN-504 interconnect configuration
This patch adds a minimal framework for Dickens CCN-504
interconnect configuration - mainly related to adding Clusters/cores
to snoop/DVM domain and setting QoS of the RN-I ports.

LS2085A platform makes use of these configurations to support
better network data performance and to boot a SMP Linux.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:37:49 -05:00
Tom Rini
b5d92ba1ad ARM: SPL: Use CONFIG_SPL_DM not CONFIG_DM
We now have the CONFIG_SPL_DM for code within SPL to toggle caring about
DM or not.  Without this change platforms that do enable CONFIG_DM but
not CONFIG_SPL_DM may be broken (such as OMAP5).

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-12 20:48:07 -04:00
Wu, Josh
633b6ccedf ARM: cache: implement a default weak flush_cache() function
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.

In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.

So in this patch remove such code in flush_cache() and only call
flush_dcache_range().

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2015-08-12 20:47:48 -04:00
Wu, Josh
387871a10e ARM: cache: add an empty stub function for invalidate/flush dcache
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.

To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-12 20:47:47 -04:00
Heiko Schocher
80402f34f8 spl, common, serial: build SPL without serial support
This patch enables building SPL without
CONFIG_SPL_SERIAL_SUPPORT support.

Signed-off-by: Heiko Schocher <hs@denx.de>
[trini: Ensure we build arch/arm/imx-common on mx28]
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-12 20:47:13 -04:00
Thierry Reding
502a2aff76 arm64: Handle arbitrary CONFIG_SYS_MALLOC_F_LEN values
The encoding of the sub instruction used to handle CONFIG_SYS_MALLOC_F_LEN
can only accept certain values, and the set of acceptable values differs
between the AArch32 and AArch64 instructions sets. The default value of
CONFIG_SYS_MALLOC_F_LEN works with either ISA. Tegra uses a non-default
value that can only be encoded in the AArch32 ISA. Fix the AArch64 crt0
assembly so it can handle completely arbitrary values.

Signed-off-by: Thierry Reding <treding@nvidia.com>
[twarren: trimmed Thierry's patch to remove changes already present]
Signed-off-by: Tom Warren <twarren@nvidia.com>
[swarren, cleaned up patch, wrote description, re-wrote subject]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-27 15:54:28 -07:00
Simon Glass
1251d51ca5 arm: Add ENTRY/ENDPROC to private libgcc functions
When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from
Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is
used to call these ARM functions, instead of plain BL, which will fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Pavel Machek <pavel@denx.de>
2015-07-07 11:39:22 +02:00
Matt Porter
f99993c108 common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()
On ARM v7M, the processor will return to ARM mode when executing
a blx instruction with bit 0 of the address == 0. Always set it
to 1 to stay in thumb mode.

Signed-off-by: Matt Porter <mporter@konsulko.com>
2015-05-28 08:18:23 -04:00
Tom Rini
4588d61a28 arch/arm/lib/bootm-fdt.c: Guard the include of <asm/armv7.h>
With d6b72da0 we started including this file unconditionally.  This
isn't allowed in a file that we also use on armv8.  This will get
cleaned up a bit better once we really start using these same features
(and have similar fdt updates needed) on armv8.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-05-14 11:07:03 -04:00
Jan Kiszka
d6b72da029 virt-dt: Allow reservation of secure region when in a RAM carveout
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.

Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons

This will be used in a subsequent patch for Jetson-TK1.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:14 -07:00
Jan Kiszka
104d6fb6cd ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditions
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.

CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:13 -07:00
Albert ARIBAUD
b939689c7b Merge branch 'u-boot/master' into 'u-boot-arm/master' 2015-05-05 10:09:06 +02:00
Tom Rini
3f6dcdb9cd Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-04-24 13:43:24 -04:00
Scott Wood
b2d5ac5985 armv8/ls2085aqds: NAND boot support
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.

Signed-off-by: Scott Wood <scottwood@freescale.com>
[York Sun: Remove +S from defconfig after commit 252ed872]
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
rev13@wp.pl
12d8a72913 ARM: Add ARMv7-M support
Signed-off-by: Kamil Lulko <rev13@wp.pl>
2015-04-22 12:14:55 -04:00
Joe Hershberger
d2eaec6006 net: Remove the bd* parameter from net stack functions
This value is not used by the network stack and is available in the
global data, so stop passing it around.  For the one legacy function
that still expects it (init op on old Ethernet drivers) pass in the
global pointer version directly to avoid changing that interface.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reported-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Trival fix to remove an unneeded variable declaration in 4xx_enet.c)
2015-04-18 11:11:11 -06:00
Joe Hershberger
0eb25b6196 common: Make sure arch-specific map_sysmem() is defined
In the case where the arch defines a custom map_sysmem(), make sure that
including just mapmem.h is sufficient to have these functions as they
are when the arch does not override it.

Also split the non-arch specific functions out of common.h

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Bryan Brinsko
97840b5d1f ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow caching
The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being
properly set to allow for the configuration specified caching modes to
be active over DRAM. This commit fixes those issues.

Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
2015-04-16 14:59:33 +02:00
Tom Rini
692e5c4e7e Merge branch 'master' of git://git.denx.de/u-boot-tegra
Conflicts:
	board/armltd/vexpress64/vexpress64.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-04-03 09:14:38 -04:00
Linus Walleij
d5f3d17ca6 armv8: semihosting: delete external interface
Now that loading files using semihosting can be done using
a command in standard scripts, and we have rewritten the boardfile
and added it to the Vexpress64, let's delete the external
interface to the semihosting file retrieveal and rely solely
on these commands, and staticize them inside that file so the
whole business is self-contained.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:46 -04:00
Linus Walleij
202a674bb8 armv8: semihosting: add a command to load semihosted images
Instead of sprinkling custom code and calls over the Vexpress64
boardfile, create a command that loads images using semihosting
just like we would load from flash memory of over the network,
using a special command:

    smhload <image> <address>

This will make it possible to remove some custom calls and
code and make the boot easier.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:45 -04:00
Linus Walleij
e769f68613 armv8: semihosting: do not inline trap call
The semihosting trap call does not like being inlined, probably
because that will mean register reordering screwing up the return
value in r0, so tag this function "noinline".

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-28 12:07:45 -04:00
David Feng
b263302aa5 ARMv8: enable pre-allocation malloc
Allocate memory space for pre-allocation malloc and zero global data.
This code is partly from crt0.S.

Signed-off-by: David Feng <fenghua@phytium.com.cn>
2015-03-27 16:28:58 +01:00
Tom Rini
b79dadf846 Merge branch 'master' of git://git.denx.de/u-boot-tegra
Conflicts:
	README

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-03-10 19:09:18 -04:00
Tom Rini
dd09f7e73c ARM: PSCI: Rework the DT handler slightly
The way the PSCI DT update happens currently means we pull in
<asm/armv7.h> everywhere, including on ARMv8 and that in turn brings in
<asm/io.h> for some non-PSCI related things that header needs to deal
with.

To fix this, we rework the hook slightly.  A good portion of
arch/arm/cpu/armv7/virt-dt.c is common looking and I hope that when PSCI
is needed on ARMv8 we can re-use this by and large.  So rename the
current hook to psci_update_dt(), move the prototype to <asm/psci.h> and
add an #ifdef that will make re-use later easier.

Reported-by: York Sun <yorksun@freescale.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: York Sun <yorksun@freescale.com>
2015-03-09 11:13:29 -04:00
Przemyslaw Marczak
114c86d826 arm: relocation: clear .bss section with arch memset if defined
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performance. This is able
thanks to the ARM multiple register instructions.

Unfortunatelly the relocation is done without the cache enabled,
so it takes some time, but zeroing the BSS memory takes much more
longer, especially for the configs with big static buffers.

A quick test confirms, that the boot time improvement after using
the arch memcpy for relocation has no significant meaning.
The same test confirms that enable the memset for zeroing BSS,
reduces the boot time.

So this patch enables the arch memset for zeroing the BSS after
the relocation process. For ARM boards, this can be enabled
in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'.

This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1384ms - before this change
-  ~888ms - after this change

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
2015-03-09 11:13:28 -04:00
Simon Glass
db910353a1 arm: spl: Allow board_init_r() to run with a larger stack
At present SPL uses a single stack, either CONFIG_SPL_STACK or
CONFIG_SYS_INIT_SP_ADDR. Since some SPL features (such as MMC and
environment) require a lot of stack, some boards set CONFIG_SPL_STACK to
point into SDRAM. They then set up SDRAM very early, before board_init_f(),
so that the larger stack can be used.

This is an abuse of lowlevel_init(). That function should only be used for
essential start-up code which cannot be delayed. An example of a valid use is
when only part of the SPL code is visible/executable, and the SoC must be set
up so that board_init_f() can be reached. It should not be used for SDRAM
init, console init, etc.

Add a CONFIG_SPL_STACK_R option, which allows the stack to be moved to a new
address before board_init_r() is called in SPL.

The expected SPL flow (for CONFIG_SPL_FRAMEWORK) is documented in the README.

Signed-off-by: Simon Glass <sjg@chromium.org>
For version 1:
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-03-04 14:55:04 -05:00
Simon Glass
fc8fdc76e7 arm: spl: Avoid setting up a duplicate global data structure
This is already set up in crt0.S. We don't need a new structure and don't
really want one in the 'data' section of the image, since it will be empty
and crt0.S's changes will be ignored.

As an interim measure, remove it only if CONFIG_DM is not defined. This
allows us to press ahead with driver model in SPL and allow the stragglers
to catch up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-04 14:55:04 -05:00
Tom Rini
1606b34aa5 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2015-02-25 18:14:18 -05:00
Masahiro Yamada
41fbbbbc71 ARM: remove jadecpu board support
This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Matthias Weisser <weisserm@arcor.de>
Acked-by: Marek Vasut <marex@denx.de>
2015-02-24 17:06:51 -05:00
York Sun
dcd468b8f4 armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack
Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using
assembly function to guarantee stack is not used before flushing is
completed. Timeout is needed for simualtor on which CCN-504 is not
implemented. Return value can be checked for timeout situation.

Change bootm.c to disable dcache instead of simply flushing, required
by flushing L3.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:46 -08:00
Albert ARIBAUD
e1cc4d31f8 Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master' 2015-02-24 07:59:38 +01:00
Andreas Bießmann
68145d4c7b common/board_f: factor out reserve_stacks
Introduce arch_reserve_stacks() to tailor gd->start_addr_sp and gd->irq_sp to
the architecture needs.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-02-17 22:52:42 +01:00
Simon Glass
23d184d2fb arm: Show relocated PC/LR in the register dump
If we don't know the relocation address, the raw values are not very useful.
Show the pre-relocation values as well as these can be looked up in
System.map, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
2015-02-03 18:42:01 +01:00
Tom Rini
aed03faa06 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-01-26 06:42:40 -05:00
Heiko Schocher
99197a9e31 arm, arm926ejs: make thumb mode compileable
in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c
when enabling CONFIG_SYS_THUMB_BUILD:

{standard input}: Assembler messages:
{standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0'
{standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0'

so, if caches are disabled, do not use this command on arm926ejs.
used on at91 in SPL, to reduce size of SPL.

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-01-19 12:49:26 +01:00
Simon Glass
480ca13e74 arm: Add warnings about using gdata
We need to get rid of this SPL-specific setting of the global_data pointer.
It is already set up in start.S immediately before board_init_f() is called,
and there may be information there that is needed (e.g. pre-reloc malloc
info).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-16 14:52:52 -05:00
Stefan Agner
75d7a0d7f1 arm: build arch memset/memcpy in Thumb2 mode
Resynchronize memcpy/memset with kernel 3.17 and build them in
Thumb2 mode (unified syntax). Those assembler files can be built
and linked in ARM mode too, however when calling them from Thumb2
built code, the stack got corrupted and the copy did not succeed
(the exact details have not been traced back). However, the Linux
kernel builds those files in Thumb2 mode. Hence U-Boot should
build them in Thumb2 mode too when CONFIG_SYS_THUMB_BUILD is set.

To build the files without warning, some assembler instructions
had to be replaced with their UAL compliant variant (thanks
Jeroen for this input).

To build the file in Thumb2 mode the implicit-it=always option need
to be set to generate Thumb2 compliant IT instructions where needed.
We add this option to the general AFLAGS when building for Thumb2.

Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
2015-01-09 10:20:22 -05:00
Ian Campbell
97a8196451 ARM: bootm: do not add PSCI to fdt when booting in secure mode.
Commit 8bc347e2ec "ARM: bootm: Allow booting in secure mode on hyp capable
systems" added the capability to select nonsec vs sec mode boot via an
environment var.

There is a subtle gotcha with this functionality, which is that the PSCI nodes
are still created in the fdt (via armv7_update_dt->fdt_psci) even when booting
in secure mode. Which means that if the kernel is PSCI aware then it will fail
to boot because it will try and do PSCI from secure world, which won't work.

This likely didn't get noticed before because the original purpose was to
support booting the legacy linux-sunxi kernels which don't understand PSCI.

To fix expose boot_nonsec (renaming with armv7_ prefix) outside of bootm.c and
use from the virt-dt code.

As well as avoiding the creation of the PSCI nodes we should also avoid
reserving the secure RAM, so do so.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2015-01-05 15:02:03 -05:00
Tom Rini
a74a4a86a5 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-01-01 15:10:39 -05:00
Linus Walleij
9be5c661be arm: semihosting: get rid of forward declarations
By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00
Linus Walleij
4e1ef15091 arm: semihosting: fix up compile bugs
There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.

The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.

Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Suggested-by: Mark Hambleton <mark.hambleton@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-12-29 07:44:06 -05:00