Remove the driver st_smic.c used in SPEAr products and the associated
config CONFIG_ST_SMI; this driver is no more used in U-Boot after the
commit 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr
support").
Fixes: 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
I am taking over responsibility for the GE board from Sebastian Reichel.
Updating the MAINTAINERS files to reflect this.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
As the lastest spear directories are removed, delete the associated entry
in the MAINTAINERS file:
- arch/arm/cpu/arm926ejs/spear/
- arch/arm/include/asm/arch-spear/
Fixes: 570c3dcfc1 ("arm: Remove spear600 boards and the rest of SPEAr support")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Output like the following is quite irritating:
=> bootefi hello
Scanning disk mmc2.blk...
No valid Btrfs found
Bad magic number for SquashFS image.
** Unrecognized filesystem type **
Scanning disk mmc1.blk...
No valid Btrfs found
Bad magic number for SquashFS image.
** Unrecognized filesystem type **
Scanning disk mmc0.blk...
No valid Btrfs found
Bad magic number for SquashFS image.
** Unrecognized filesystem type **
Albeit a whole disk may be formatted with a filesystem in most cases
a partition table is used and the whole disk (partition number 0) doesn't
contain a filesytem. Some partitions may only contain a blob. Not seeing a
filesytem on the whole disk or on any partition is only worth a debug
message.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Our mailmapper script required Python 2 which is no longer maintained.
A main difference when converting to Python 3 is that byte strings are not
character strings. So add conversion and skip over conversion errors.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tpm test cases relies on tpm device setup. Provide an environment
variable "env__tpm_device_test_skip = True" to skip the test case
if tpm device is not present.
Only needed will have to add variable to the py-test framework.
Test runs successfully even this variable is absent.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The KBUILD_BASENAME contains just the name of the compiled module,
in this case 'sequencer', rather than a full path to the compiled
file. Use it to prevent pulling the full path into the U-Boot binary,
which is useless and annoying.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The DM DWMAC driver is perfectly capable of configuring the ethernet
PHY reset GPIO, let the driver do it instead of doing it in the board
file.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The Designware I2C IP is used to communicate with I2C peripherals on
SoCFPGA, and required to access I2C EEPROM on this board. Enable it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The WDT on this system should be enabled, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The SPI NOR bus mode is 0 on this system, update it accordingly.
Increase frequency to 40 MHz and enable SFDP parsing, since the
flashes on this system support that and it is a huge performance
improvement.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This was configured in downstream, so it is likely that most of the
custom software used around the device depends on it. Make upstream
compatible.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Increase the environment size from 4k to 16k to prevent
environment from becoming full.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
The comment is no longer meaningful due to DT conversion, drop it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This adds support for the DWC_sub31 controllers such as those
found on Apple's M1 SoC. This version of the controller
seems to work fine with the existing driver.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Allow using different PHY interfaces for multiple USB controllers. When no
value is set in DT, we fall back to CONFIG_MXC_USB_PORTSC for now to stay
compatible with current board configurations.
This also adds support for the HSIC mode of the i.MX7.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
These definitions are unused, all boards that define portsc flags use
the equivalent PORT_* definitions instead.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
The MXC_EHCI_MODE_ definitions are redundant. Replace MXC_EHCI_MODE_SERIAL
with the equivalent PORT_PTS_SERIAL.
Only the zmx25 platform is affected.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Import usb_phy_interface enum values and DT match strings from the Linux
kernel.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Pine H64 and Orange Pi 3 both provide a USB3 type A port.
Enable it in U-Boot.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Some platforms, like the Allwinner H6, do not have a separate glue layer
around the dwc3. Instead, they rely on the clocks/resets/phys referenced
from the dwc3 DT node itself. Add support for enabling the clocks/resets
referenced from the dwc3 DT node.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Resetting an XHCI controller inside xhci_register undoes any register
setup performed by the platform driver. And at least on the Allwinner
H6, resetting the XHCI controller also resets the PHY, which prevents
the controller from working. That means the controller must be taken out
of reset before initializing the PHY, which must be done before calling
xhci_register.
The logic in the XHCI core was added to support the Raspberry Pi 4
(although this was not mentioned in the commit log!), which uses the
xhci-pci platform driver. Move the reset logic to the platform driver,
where it belongs, and where it cannot interfere with other platform
drivers.
This also fixes a failure to call reset_free if xhci_register failed.
Fixes: 0b80371b35 ("usb: xhci: Add reset controller support")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This driver is needed for XHCI to work on the Allwinner H6 SoC. The
driver is copied from Linux v5.10.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.
Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.
The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.
Fixes: b73e8bf453 ("arm: stm32mp: add defconfig for trusted boot with FIP")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
reset_*_bulk expects a real pointer.
Fixes: 4f7abafe1c ("driver: watchdog: reset watchdog in designware_wdt_stop() function")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
part of an official release before it is agreed.
-----BEGIN PGP SIGNATURE-----
iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAmFFvvURHHNqZ0BjaHJv
bWl1bS5vcmcACgkQfxc6PpAIreZvvwgAxZdHdfMrG4gwfMKVVvDxvopglpJbNB6W
w0Rc/m48dykcLV4LfVFCXBEvFARSXkejqsVFVwTvN8V/k1qF3bVTQjcVMz9ExWK0
78k4hfCytR2/ydcD48vaVTaJVh8ee/c8hKRrHoFLinc7vOebkDY1CV/9pPNrBA+m
yFO78cQ8sgsRJGS/HbXsQsCvpVmViLGEqX1AZ15PU0htN5PicZNkkj/gxjpoaiBR
NV95v7K//eHPn0S9v5DlqF2ffn0tKwnolPoPcRjPTppet1KbtTSaMCLpIKq33TsM
ssKjUbS3pWZfOmfs+z9/jh/fpXXACwxBBgK6FCrMhPE6I6Fslno9lA==
=XFMN
-----END PGP SIGNATURE-----
Merge tag 'dm-pull-18sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm
Revert the public-key-embedded-in-executable patches so this does not form
part of an official release before it is agreed.
This was unfortunately applied despite much discussion about it beiong
the wrong way to implement this feature.
Revert it before too many other things are built on top of it.
This reverts commit ddf67daac3.
Signed-off-by: Simon Glass <sjg@chromium.org>
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.
However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.
As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.
To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.
We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.
Signed-off-by: Nishanth Menon <nm@ti.com>
NB0 is bridge to SRAM and NB1 is bridge to DDR.
To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).
This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.
This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.
Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: Nishanth Menon<nm@ti.com>
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
There are three different divider values in the DIV_CTRL register
controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
function writes the entire register when programming plld, even though
plld only resides in the lower 6 bits.
Change the plld programming to read-modify-write to only affect the
relevant bits for plld and to preserve the other two divider values
present in the upper 16 bits, otherwise they will always get set to zero
when programming plld.
Fixes: 0aa2930ca1 ("clk: add support for TI K3 SoC PLL")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.
Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.
The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.
Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
The common TI SCI header file uses some macros from err.h and these
get exercised when CONFIG_TI_SCI_PROTOCOL is not defined. Include
the linux/err.h header file in this header file directly rather
than relying on source files to include it to eliminate any
potential build errors.
While at this, reorder the existing header file include to the
beginning of the file.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Ivan's patch fixes a kernel warning when booting RPi2, as the firmware
already
provides a frambebuffer node.
Marek's patch fixes random crashes on 32 bit RPi4 with newer firmware.
My SMBIOS patchesfixes an issue that show up with
e4f8e543f1 ("smbios: Drop the unused Kconfig options").
Basically the SMBIOS table broke and wasn't readable anymore.
It appears that RPi firmware has already added framebuffer
node under /chosen, at least on RPi 2 versions. So check
for this and don't add duplicate node.
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Move the XHCI PCI device base up in the virtual address space. This fixes
initialization failure observed with newer Raspberry Pi firmware, later
than 63b1922311 ("firmware: arm_loader: Update armstubs with those from
PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base
conflicts with the updated ARM/VideoCore firmware.
This also requires to reduce the size of the mapped PCI device region
from 8MiB to 4MiB to fit into 32bit address space. This is still enough
for the XHCI PCI device.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Enable this driver to allow U-Boot to get SMBIOS table information from
a device tree node.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Fabian Vogt <fvogt@suse.com>
At present SMBIOS tables are empty, which breaks some use-cases that
rely on that. Add some minimal information to fulfill this.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
