Commit graph

62293 commits

Author SHA1 Message Date
Tom Rini
533c9f5714 Merge tag '20191217-for-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
i2c: for next
- misc: i2c_eeprom:
  Add partition support and add ability to query size
  of eeprom device and partitions
- i2c common:
  add support for offset overflow in to address and add
  sandbox tests for it.
2019-12-17 07:53:08 -05:00
Tudor Ambarus
96b225b0c8 configs: sama5d27_wlsom1_ek: mmc: Enable SPI NOR ethaddr retrieval
Enable the SPI NOR SFDP support and the Microchip QSPI driver.
CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser,
and for the SST case, the retrieval of the ethaddr from the
SPI NOR flash.

While touching the SPI NOR logic, sync with the
sama5d27_wlsom1_ek_qspiflash_defconfig and enable
CONFIG_SPI_FLASH_SPANSION.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-12-17 09:49:05 +02:00
Tudor Ambarus
3dbd23e8c3 configs: sama5d27_wlsom1_ek: qspiflash: Enable SPI NOR ethaddr retrieval
CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser,
and for the SST case, the retrieval of the ethaddr from the
SPI NOR flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-12-17 09:49:05 +02:00
Tudor Ambarus
f10b4006a6 board: atmel: sama5d27_wlsom1_ek: Set ethaddr from spi-nor flash
The SST26VF064BEUI spi-nor flash is programmed at the factory with a
globally unique address stored in the SFDP vendor parameter table and
it is permanently writeprotected. Retrieve the EUI-48 address and set it
as ethaddr env.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2019-12-17 09:49:05 +02:00
Tudor Ambarus
a11c081da3 mtd: spi: spi-nor-core: Add SST vendor specific SFDP parser
JESD216 allow vendors to define their own SFDP tables.

Add SST SFDP parser. The vendor table is allocated using resource-managed
kmalloc - the table will be freed on driver detach. It will be accessible
by getting the UCLASS_SPI_FLASH's private data.

The SST's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-17 09:49:05 +02:00
Robert Beckett
033e18b47b misc: i2c_eeprom: add size query
Add ability to query size of eeprom device and partitions

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:58:19 +01:00
Robert Beckett
1a59cb426d misc: i2c_eeprom: add fixed partitions support
Add ability to partition eeprom via devicetree bindings

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:58:16 +01:00
Robert Beckett
951674ac7e dm: i2c: EEPROM simulator add tests for addr offset mask
Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:57:31 +01:00
Robert Beckett
22e93511be dm: i2c: EEPROM simulator allow tests visibility of addr and offset
Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.

Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:57:22 +01:00
Robert Beckett
85968522b9 i2c: add support for offset overflow in to address
Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.

Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Signed-off-by: Ian Ray <ian.ray@ge.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-12-17 06:57:12 +01:00
Tom Rini
ef7c2af659 Prepare v2020.01-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-16 07:39:56 -05:00
Simon Glass
a1d6dc3f84 x86: Add chromebook_coral
Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:30 +08:00
Simon Glass
2153e8fbfc x86: apl: Add FSP support
The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:30 +08:00
Simon Glass
a9a4b685de x86: apl: Add FSP structures
These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:30 +08:00
Simon Glass
1fc5419314 x86: apl: Add Kconfig and Makefile
Add basic plumbing to allow Apollo Lake support to be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:29 +08:00
Simon Glass
46c674bfde x86: apl: Add P2SB driver
Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:29 +08:00
Simon Glass
4dc0ab3551 x86: apl: Add SPL/TPL init
Add code to init the system both in TPL and SPL. Each phase has its own
procedure.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:29 +08:00
Simon Glass
6a4c237af9 x86: apl: Add a CPU driver
Add a bare-bones CPU driver so that CPUs can be probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:29 +08:00
Simon Glass
409d4c6fe9 x86: apl: Add SPL loaders
Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:29 +08:00
Simon Glass
e82c624d7c spl: Add methods to find the position/size of next phase
Binman supports writing the position and size of U-Boot proper and SPL
into the previous phase of U-Boot. This allows the next phase to be easily
located and loaded.

Add functions to return these useful values, along with symbols to allow
TPL to load SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:28 +08:00
Simon Glass
f5b18ae309 x86: apl: Add PUNIT driver
Add a driver for the Apollo Lake P-unit (power unit). It is modelled as a
syscon driver since it only needs to be probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:28 +08:00
Simon Glass
40fb08e917 x86: apl: Add PCH driver
Add a driver for the Apollo Lake Platform Controller Hub. It does not have
any functionality and is just a placeholder for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:28 +08:00
Simon Glass
8bd5dcd895 x86: apl: Add LPC driver
This driver the LPC and provides a few functions to set up LPC features.
These should probably use ioctls() or perhaps, better, have specific
uclass methods.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:28 +08:00
Simon Glass
3a02f699fa x86: apl: Add ITSS driver
This driver models some sort of interrupt thingy but there are so many
abreviations that I cannot find out what it stands for. Possibly something
to do with interrupts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:27 +08:00
Simon Glass
e5fb75c9ba x86: apl: Add hostbridge driver
This driver models the hostbridge as a northbridge. It simply sets up the
graphics BAR. It supports of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:27 +08:00
Simon Glass
bd47209743 x86: apl: Add systemagent driver
This driver handles communication with the systemagent which needs to be
told when U-Boot has completed its init.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:27 +08:00
Simon Glass
070a946008 i2c: designware: Add Apollo Lake support
For Apollo Lake we need to take the I2C bus controller out of reset before
using this. Add this functionality to the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:27 +08:00
Simon Glass
0a6f333e8d x86: apl: Add pinctrl driver
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the
common Intel pinctrl support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:26 +08:00
Simon Glass
7656582378 x86: apl: Add UART driver
Add a driver for the Apollo Lake UART. It uses the standard ns16550 device
but also sets up the input clock with LPSS and supports configuration via
of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:26 +08:00
Simon Glass
28eefefccf x86: apl: Add PMC driver
Add a driver for the Apollo Lake SoC. It supports the basic operations and
can use device tree or of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:26 +08:00
Simon Glass
5690d5c8f8 x86: apl: Add basic IO addresses
Add some fixed IO and mmap addresses for use in the device tree and with
some early-init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:26 +08:00
Simon Glass
baaeb92c21 x86: Move qemu CPU fixup function into its own file
This function is specific to qemu so it seems best to keep it separate
from the generic code.

Move it out to a new file and update the condition to use if() instead of
 #ifdef

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
7e589bc19b x86: Add a generic Intel GPIO driver
Add a GPIO driver which uses the pinctrl driver to access the pad
information. This driver relies on the GPIO nodes being subnodes to the
pinctrl device.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
74749f1e84 x86: Add a generic Intel pinctrl driver
Recent Intel SoCs share a pinctrl mechanism with many common elements. Add
an implementation of this core functionality, allowing SoC-specific
drivers to avoid adding common code.

As well as a pinctrl driver this provides a GPIO driver based on the same
code.

Once other SoCs use this driver we may consider moving more properties to
the device tree (e.g. the community info and pad definitions).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
b84d4d0932 x86: Add low-power subsystem (lpss) support
This subsystem is present on various Intel SoCs.

Add very basic support for taking an lpss device out of reset.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:25 +08:00
Simon Glass
e556d3d630 x86: Enable pinctrl in SPL and TPL
If these phases are used we typically want to enable pinctrl in then, so
that pad setup and GPIO access are possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:24 +08:00
Simon Glass
4806fcea1a mtd: spi: Export spi_flash_std_probe()
With of-platdata we need to create drivers for particular chips, or at
least drivers that are separate from the standard code, since C structures
are created by dtoc which are private to that driver.

To avoid duplicating the probing code, export this probe function for use
by these drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:24 +08:00
Simon Glass
3937df3d6c spi: ich: Add Apollo Lake support
Add support for Apollo Lake to the ICH driver. This involves adjusting the
mmio address and skipping setting of the bbar.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:24 +08:00
Simon Glass
636555a4c4 spi: ich: Add TPL support
In TPL we want to reduce code size and support running with CONFIG_PCI
disabled. Add special code to handle this using a fixed BAR programmed
into the SPI on boot. Also cache the SPI flash to speed up boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:24 +08:00
Simon Glass
92842147c3 spi: ich: Add support for get_mmap() method
Add this method so that the memory-mapped location of the SPI flash can
be queried.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
1facebd18f spi: ich: Support hardware sequencing
Apollo Lake (APL) only supports hardware sequencing. Add support for this
into the SPI driver, as an option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
0d3ee3e199 spi: ich: Support of-platdata for fast-spi
The Intel Fast SPI interface is similar to ICH. Add of-platdata support
for this using the "intel,fast-spi" compatible string.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
43c145b8b3 spi: ich: Correct max-size bug in ich_spi_adjust_size()
This incorrectly shortens read operations if there is a maximum write size
but no maximum read size. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:23 +08:00
Simon Glass
c59f2ac175 dm: doc: Add a note about of-platdata and header files
We don't want to include dt-structs.h in header files, so add a note about
that.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
75214b051b spi: ich: Add mmio_base to struct ich_spi_platdata
It is useful to store the mmio base in platdata. It reduces the amount of
casting needed. Update the code and move the struct to the C file at the
same time, as we will need to use with of-platdata.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
a550662c27 spi: ich: Various small tidy-ups
Use debug() instead of printf() to reduce code size and change a bool
return value to the use the 'bool' type. Also drop the global data
declaration since it not actually used. Finally, set the log category.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
b47aa26eb9 spi: ich: Fix header order
Move the header files into the right order.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
702b28a163 spi: ich: Convert to livetree
Use dev_get_driver_data() to obtain the device type. It has the same
effect and is shorter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:22 +08:00
Simon Glass
17e754492f spi: ich: Move the protection/lockdown code into a function
Reduce the size of the probe function but putting this code into its own
function.

Also remove the assumption that the PCH is always a parent of the SPI
controller, as this is not the case APL platforms. Use driver model to
find the PCH instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:21 +08:00
Simon Glass
674990c0dc spi: ich: Move init function just above probe()
It is annoying to have some of the init code in a different part of the
file. Move ich_init_controller() to just above probe() to keep things
together.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:21 +08:00