Commit graph

1082 commits

Author SHA1 Message Date
Heinrich Schuchardt
9c6d050966 doc: document sbi command
Add a man-page for the sbi command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-01-25 01:15:33 +01:00
Kate Liu
34a5addb7b board: presidio: Add Parallel NAND support
Set environment for Nand flash (U-boot 2020.04):
- add nand flash in the device tree
- add new default configuration file for G3 using parallel Nand
- set nand parameters in presidio_asic.h

Signed-off-by: Kate Liu <kate.liu@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18 15:14:37 -05:00
Kate Liu
161df94b3c mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC support
Add Cortina Access parallel Nand support for CAxxxx SOCs

Signed-off-by: Kate Liu <kate.liu@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
CC: Scott Wood <oss@buserror.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-01-18 15:14:34 -05:00
Michal Simek
b66d7af41f video: seps525: Add seps525 SPI driver
Add support for the WiseChip Semiconductor Inc. (UG-6028GDEBF02) display
using the SEPS525 (Syncoam) LCD Controller. Syncoam Seps525 PM-Oled is RGB
160x128 display. This driver has been tested through zynq-spi driver.

ZynqMP> load mmc 1 100000 rainbow.bmp
61562 bytes read in 20 ms (2.9 MiB/s)
ZynqMP> bmp info 100000
Image size    : 160 x 128
Bits per pixel: 24
Compression   : 0
ZynqMP> bmp display 100000
ZynqMP> setenv stdout vidconsole

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-05 11:54:53 +01:00
Vikhyat Goyal
1ac1a04b9e video: seps525: Add dt binding description
Added dt binding for seps525 display driver.

Signed-off-by: Vikhyat Goyal <vikhyat.goyal@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-05 11:54:53 +01:00
Tom Rini
46a4d75203 Pull request for UEFI sub-system for efi-2021-01-rc4
* Provide a tool to create a file with UEFI variables to preseed UEFI
   variable store.
 * Make size of UEFI variable store configurable.
 * Add man pages for commands 'bootefi' and 'button'.
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Merge tag 'efi-2021-01-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2021-01-rc4

* Provide a tool to create a file with UEFI variables to preseed UEFI
  variable store.
* Make size of UEFI variable store configurable.
* Add man pages for commands 'bootefi' and 'button'.
2020-12-20 14:55:59 -05:00
Heinrich Schuchardt
77504ee676 MAINTAINERS: add tools/efivar.py to EFI PAYLOAD
tools/efivar.py allows to prepare a file with UEFI variables to preseed
the UEFI variable store.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-20 17:40:06 +01:00
Heinrich Schuchardt
0c1b71cd07 doc: man-page for bootefi command
Provide a description of the bootefi command.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-12-20 17:40:06 +01:00
Pengpeng Chen
24f2794232 spi: ca_sflash: Add CAxxxx SPI Flash Controller
Add SPI Flash controller driver for Cortina Access
CAxxxx SoCs

Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Vignesh R <vigneshr@ti.com>
CC: Tom Rini <trini@konsulko.com>
[jagan: rebase on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-12-18 16:16:37 +05:30
Patrice Chotard
5905e0880a MAINTAINERS: Update ARM STI and ARM STM STM32MP Arch maintainers emails
Update Patrick and my email address with the one dedicated to
upstream activities.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-09 10:57:50 +01:00
Heinrich Schuchardt
e405efcf4b MAINTAINERS: assign include/log.h
include/log.h belongs to LOGGING.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-12-02 16:21:58 -05:00
Sean Anderson
72eda5074b lib: Add getopt
Some commands can get very unweildy if they have too many positional
arguments. Adding options makes them easier to read, remember, and
understand.

This implementation of getopt has been taken from barebox, which has had
option support for quite a while. I have made a few modifications to their
version, such as the removal of opterr in favor of a separate getopt_silent
function. In addition, I have moved all global variables into struct
getopt_context.

The getopt from barebox also re-orders the arguments passed to it so that
non-options are placed last. This allows users to specify options anywhere.
For example, `ls -l foo/ -R` would be re-ordered to `ls -l -R foo/` as
getopt parsed the options. However, this feature conflicts with the const
argv in cmd_tbl->cmd. This was originally added in 54841ab50c ("Make sure
that argv[] argument pointers are not modified."). The reason stated in
that commit is that hush requires argv to stay unmodified. Has this
situation changed? Barebox also uses hush, and does not have this problem.
Perhaps we could use their fix?

I have assigned maintenance of getopt to Simon Glass, as it is currently
only used by the log command. I would also be fine maintaining it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-30 10:56:11 -04:00
Tom Rini
47754334b1 Xilinx changes for v2021.01-v2
common:
 - Add support for 64bit loadables from SPL
 
 xilinx:
 - Update documentation and record ownership
 - Enable eeprom board detection based legacy and fru formats
 - Add support for FRU format
 
 microblaze:
 - Optimize low level ASM code
 - Enable SPI/I2C
 - Enable distro boot
 
 zynq:
 - Add support for Zturn V5
 
 zynqmp:
 - Improve silicon detection code
 - Enable several kconfig options
 - Align DT with the latest state
 - Enabling security commands
 - Enable and support FPGA loading from SPL
 - Optimize xilinx_pm_request() calling
 
 versal:
 - Some DTs/Kconfig/defconfig alignments
 - Add binding header for clock and power
 
 zynq-sdhci:
 - Add support for tap delay programming
 
 zynq-spi/zynq-qspi:
 - Use clock framework for getting clocks
 
 xilinx-spi:
 - Fix some code issues (unused variables)
 
 serial:
 - Check return value from clock functions in pl01x
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Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x
2020-10-29 11:30:15 -04:00
Andre Przywara
5a4a891e04 MAINTAINERS, git-mailrc: Update sunxi maintainers
Maxime mentioned that he feels not having the time to be an Allwinner
maintainer anymore. Take over from him.

Maxime, many thanks for your great work in the past! I hope I can still
relay the occasional technical question to you in the future.

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2020-10-29 09:57:13 -04:00
Heinrich Schuchardt
87e9963d5a rtc: provide an emulated RTC
On a board without hardware clock this software real time clock can be
used. The build time is used to initialize the RTC. So you will have
to adjust the time either manually using the 'date' command  or use
the 'sntp' to update the RTC with the time from a network time server.
See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is
advanced according to CPU ticks.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 21:13:15 +01:00
Michal Simek
79d4204f72 MAINTAINERS: Record documentation for Xilinx platforms
Add fragment to cover documenation for Xilinx platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-10-27 08:01:36 +01:00
Sean Anderson
47d7e3b5eb riscv: Move timer portions of SiFive CLINT to drivers/timer
Half of this driver is a DM-based timer driver, and half is RISC-V-specific
IPI code. Move the timer portions in with the other timer drivers. The
KConfig is not moved, since it also enables IPIs. It could also be split
into two configs, but no boards use the timer but not the IPI atm, so I
haven't split it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 10:01:28 +08:00
Sean Anderson
79b135f1f9 riscv: Move Andes PLMT driver to drivers/timer
This is a regular timer driver, and should live with the other timer
drivers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 10:01:28 +08:00
Robert Marko
033ec636fc rng: Add Qualcomm MSM PRNG driver
Add support for the hardware pseudo random number generator found in Qualcomm SoC-s.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
975151d056 net: Add IPQ40xx MDIO driver
This adds the driver for the IPQ40xx built-in MDIO.
This will be needed to support future PHY driver.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Robert Marko
367ea426a5 spi: Add Qualcomm QUP SPI controller driver
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s.

Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW.
FIFO and Block modes are supported, no support for DMA mode is planned.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-10-22 09:54:54 -04:00
Tom Rini
b90daf2743 - Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
 - Update MAINTAINERS for ARM STM STM32MP
 - Manage eth1addr on dh board with KS8851
 - Limit size of cacheable DDR in pre-reloc stage in stm32mp1
 - Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
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Merge tag 'u-boot-stm32-20201021' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Activate CMD_EXPORTENV/CMD_IMPORTENV/CMD_ELF for STM32MP15 defconfig
- Fix stm32prog command: parsing of FlashLayout without partition
- Update MAINTAINERS for ARM STM STM32MP
- Manage eth1addr on dh board with KS8851
- Limit size of cacheable DDR in pre-reloc stage in stm32mp1
- Use mmc_of_parse() to read host capabilities in mmc:sdmmc2 driver
2020-10-22 08:25:41 -04:00
Patrick Delaunay
2bf692d317 MAINTAINERS: Add STM32MP1 RNG driver in stm32mp platform
Add the STM32MP1 RNG driver in the list of drivers supported by
the STMicroelectronics STM32MP15x series.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Patrick Delaunay
ce52023050 MAINTAINERS: Add stm32 and stm regexp for ARM STM STM32MP platform
Add files and directories regex "stm32" and "stm" in "ARM STM STM32MP"
platform to avoid missing files or drivers supported by the
STMicroelectronics series STM32MP15x.

This patch adds the rules already used in Linux kernel for
ARM/STM32 ARCHITECTURE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-10-21 18:12:20 +02:00
Chunfeng Yun
0cd791ced9 MAINTAINERS: add USB driver to ARM MEDIATEK
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK,
and add myself as a maintainer for it.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-10-20 00:49:05 +02:00
Sean Anderson
7224d5ccf8 pinctrl: Add support for Kendryte K210 FPIOA
The Fully-Programmable Input/Output Array (FPIOA) device controls pin
multiplexing on the K210. The FPIOA can remap any supported function to any
multifunctional IO pin. It can also perform basic GPIO functions, such as
reading the current value of a pin. However, GPIO functionality remains
largely unimplemented (in favor of the dedicated GPIO peripherals).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Sean Anderson
7f0f1806e3 test: pinmux: Add test for pin muxing
This extends the pinctrl-sandbox driver to support pin muxing, and adds a
test for that behaviour. The test is done in C and not python (like the
existing tests for the pinctrl uclass) because it needs to call
pinctrl_select_state.  Another option could be to add a command that
invokes pinctrl_select_state and then test everything in
test/py/tests/test_pinmux.py.

The pinctrl-sandbox driver now mimics the way that many pinmux devices
work.  There are two groups of pins which are muxed together, as well as
four pins which are muxed individually. I have tried to test all normal
paths. However, very few error cases are explicitly checked for.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-08 11:42:36 -04:00
Heinrich Schuchardt
b0b3524d94 MAINTAINERS: assign doc/arch/sandbox.rst
Add doc/arch/sandbox.rst to the scope of SANDBOX.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-06 09:07:54 -06:00
Tom Rini
caebff09ef First set of u-boot-atmel features for 2021.01 cycle
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Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next

First set of u-boot-atmel features for 2021.01 cycle:

This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update.  The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
2020-10-05 10:54:27 -04:00
Claudiu Beznea
01c35f269f cpu: at91: add driver for CPU
Add basic CPU driver use to retrieve information about CPU itself.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-10-05 10:45:16 +03:00
Claudiu Beznea
96b9a5cdf8 MAINTAINERS: add Microchip PIT64B timer
Add Microchip PIT64B timer.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-28 14:07:26 +03:00
Tom Rini
751b18b8a1 Merge branch 'master' into next
Merge in v2020.10-rc5
2020-09-21 14:25:37 -04:00
Robert Marko
dec042028e phy: add driver for Qualcomm IPQ40xx USB PHY
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs.
The driver sets up HS and SS phys.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Robert Marko
8ef7df5df3 reset: Add IPQ40xx reset controller driver
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-18 16:20:47 -04:00
Miquel Raynal
c4d0384a4a MAINTAINERS: add myself as reviewer for SquashFS
I also followed the development of the SquashFS support in U-Boot
as part of Joao Marcos internship, so I would also appreciate receiving
new contributions and bug reports related to this topic.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-09-16 16:54:00 -04:00
Thomas Petazzoni
42ef2edc85 MAINTAINERS: add myself as reviewer for SquashFS
As I have followed the development of the SquashFS support in U-Boot
as part of Joao Marcos work, it makes sense to get Cc'ed on
contributions/bug reports related to the squashfs support.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
2020-09-16 16:54:00 -04:00
Baruch Siach
a8a71c9488 MAINTAINERS: update clk entry git tree
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-09-16 16:54:00 -04:00
Robert Marko
a5fc58734f dt-bindings: clock: import Qualcomm IPQ4019 bindings
Import Qualcomm IPQ4019 GCC bindings from Linux.
This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-09-09 16:57:36 -04:00
Rayagonda Kokatanur
975d2a6980 MAINTAINERS: update maintainers file for new files
Update MAINTAINERS file for new files.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 16:57:35 -04:00
Qu Wenruo
b737c822c0 MAINTAINERS: Add btrfs mailing list and myself as reviewer
Since the current code base is mostly from btrfs-progs, anyone
contributing to U-Boot btrfs code could also help us to improve
btrfs-progs and btrfs kernel module.

Also add myself as designated reviewer.

Signed-off-by: Qu Wenruo <wqu@suse.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-09-07 21:00:36 -04:00
Masahiro Yamada
23e333a5c0 MAINTAINERS: step down as maintainer of UniPhier SoCs
I am leaving Socionext. Orphan the UniPhier platform until somebody
takes the role.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-08-31 17:11:24 -04:00
Anastasiia Lukianenko
607274f7f6 MAINTAINERS: Add maintainers to XEN section
Signed-off-by: Anastasiia Lukianenko <anastasiia_lukianenko@epam.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-24 14:11:31 -04:00
Chia-Wei, Wang
aff987c457 MAINTAINERS: Add maintainers for Aspeed SoCs
Update maintainers for Aspeed SoC platforms.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
2020-08-14 09:46:40 -04:00
Jway Lin
047e31ed4b led: led_cortina: Add CAxxx LED support
Add Cortina Access LED controller support for CAxxxx SOCs

Signed-off-by: Jway Lin <jway.lin@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Simon Glass <sjg@chromium.org>

Add head file fixed link error and remove unused flashing function
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-07 22:31:32 -04:00
Joao Marcos Costa
f428e33b6b test/py: Add tests for the SquashFS commands
Add Python scripts to test 'ls' and 'load' commands. The scripts
generate a SquashFS image and clean the directory after the assertions,
or if an exception is raised.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-07 22:31:32 -04:00
Joao Marcos Costa
bba604b65e fs/squashfs: add filesystem commands
Add 'ls' and 'load' commands.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-07 22:31:32 -04:00
Joao Marcos Costa
c510061303 fs/squashfs: new filesystem
Add support for SquashFS filesystem. Right now, it does not support
compression but support for zlib will be added in a follow-up commit.

Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
2020-08-07 22:31:32 -04:00
Rayagonda Kokatanur
1c085cc657 MAINTAINERS: update maintainers for broadcom ns3 platform
Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3).

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:37:11 -04:00
Stefan Bosch
b39cacc268 arm: add (default) config for nanopi2 board
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- Configuration changed, mainly several "CONFIG_..." moved from
  s5p4418_nanopi2.h to s5p4418_nanopi2_defconfig and USB related
  configs removed because USB is not supported yet.
- s5p4418_nanopi2.h: "CONFIG_" removed from several s5p4418/nanopi2
  specific defines because the appropriate values do not need to be
  configurable.
- pinctrl is supported now, therefore "CONFIG_PINCTRL=y" added to
  s5p4418_nanopi2_defconfig.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29 08:43:40 -04:00
Robert Marko
e479a7d52e arm: Add support for Qualcomm IPQ40xx family
This introduces initial support for the popular Qualcomm
IPQ40x8 and IPQ40x9 WiSoC series.

IPQ40xx series have 4x Cortex A7 ARM-v7A cores.
Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029.

IPQ40x8 and IPQ40x9 use the same cores, but differ in
addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8)
and supported peripherals (IPQ40x8 lacks RGMII, LCD controller
and EMMC/SDHCI controllers).

IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only
by their rated temperatures rates with IPQ402X models being
rated for wider temperature ranges.

Initially this supports:
* Simple clock driver (Only for UART1 now, will be extended)
* Pinctrl driver (Supports UARTX and GPIO now, will be extended)
* GPIOs already supported by msm_gpio driver with updates
* UARTs already supported by serial_msm driver with updates

Further peripherals will come in later patches.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2020-07-29 08:43:40 -04:00