Commit graph

4 commits

Author SHA1 Message Date
Kever Yang
64a524b08a rockchip: rk3036: sync os_reg2 define with other soc
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-11 12:13:48 +02:00
Lin Huang
99aaa93075 rockchip: rk3036: change ddr frequency to 400M
emac may use dpll as clock parent, and it request the clock frequency
multiples of 50, so change ddr frequency to 400M.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-10 08:32:01 -07:00
huang lin
e390680015 rockchip: rk3036 sdram setting cs1_row when rank larger than 1
only rank large than 1, we will use cs1_row, so check rank, when
rank larger than 1, we set the cs1_row.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-13 20:51:44 -07:00
huang lin
53c45f0ca2 rockchip: add rk3036 sdram driver
add rk3036 sdram driver so we can set up sdram in SPL

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-12-01 08:07:22 -07:00