Commit graph

47942 commits

Author SHA1 Message Date
Patrice Chotard
003b4c1e76 ARM: DTS: add STM32F469 Discovery board support
This DT file comes from kernel v4.15-rc1

stm32f469-pinctrl.dtsi header has been updated with correct
STMicroelectronics Copyright.

Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:47 -05:00
Patrice Chotard
0b3f789ad1 ram: stm32: add memory mapping selection support
This allows to controls the memory internal mapping at
address 0x0000 0000.
We can either map at 0x0000 0000 :
  _ main flash memory
  _ system flash memory
  _ FMC bank1 (NOR/PSRAM 1 and 2)
  _ embedded SRAM
  _ FMC/SDRAM bank1

This is needed for future STM32F469-disco board

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:47 -05:00
Patrice Chotard
c8f787760e board: stm32f429-disco: switch to DM STM32 pinctrl and gpio driver
Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers
instead of board GPIO initialization.

Remove stm32_gpio.c which is no more used and migrate
structs stm32_gpio_regs and stm32_gpio_priv into
arch-stm32f4/gpio.h to not break compilation.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:46 -05:00
Patrice Chotard
4a56fd484a board: stm32f429-disco: switch to DM STM32 clock driver
Use available DM clk_stm32f.c driver instead of dedicated
mach-stm32/stm32f4/clock.c.

Migrate periph_clock defines from stm32_periph.h directly in
CLK driver. These periph_clock defines will be removed when STMMAC,
TIMER2 and SYSCFG drivers will support DM CLK.

Enable also CLK flag.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:46 -05:00
Patrice Chotard
dcb11959d8 mach-stm32: stmf32f4: timer: remove clock_get() call
In order to use common clock driver between STM32F4 and
STM32F7, remove clock_get() call
As APB_PSC is always set to 2, only case when
clock_get(CLOCK_AHB) != clock_get(CLOCK_APB1) is kept

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:46 -05:00
Patrice Chotard
2d18d72858 board: stm32f429-disco: switch to DM STM32 serial driver
Remove serial_stm32.c driver and uart init from board file,
use available DM serial_stm32x7.c driver compatible for
STM32F4/F7 and H7 SoCs.

The serial_stm32x7.c driver will be renamed later with a more
generic name as it's shared with all STM32 Socs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:46 -05:00
Patrice Chotard
a05707004d configs: stm32f429-disco: enable MISC, STM32_RCC, DM_RESET and STM32_RESET
This allows to support rcc MFD driver.
By enabling all these flags, we need to increase malloc area to avoid
crash during early stage.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:46 -05:00
Patrice Chotard
98693c22d9 pinctrl: stm32: add stm32f4 pinctrl compatible strings
STM32F4 SoCs uses the same pinctrl block as found into
STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl"
compatible string into pinctrl_stm32.c.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:45 -05:00
Patrice Chotard
7fd65ef552 board: stm32f429-discovery: switch to DM STM32 sdram driver
Use available DM stm32_sdram.c driver instead of board
SDRAM initialization.
For that, enable OF_CONTROL, OF_EMBED and STM32_SDRAM flags.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:45 -05:00
Patrice Chotard
791651e390 ARM: DTS: stm32: add stm32f429-disco-u-boot dts file
_ Add gpio compatible and aliases for stm32f429

_ Add FMC sdram node with associated new bindings value to
  manage second bank (ie bank 1).

_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
  pwrcfg and gpio nodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:45 -05:00
Patrice Chotard
46b1e54b18 ARM: DTS: stm32: add STM32F429 SoC and its Discovery board support
All these files comes from kernel v4.15-rc1.

Update some header with correct STMicroelectronics Copyright.

Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-01-10 08:05:45 -05:00
Chris Packham
0a05bf42b4 ARM: mvebu: correct reference for "ethernet1" on DB-88F6820-AMC
The DB-88F6820-AMC connects ethernet@34000 and ethernet@70000 which are
labeled as eth2 and eth0 in armada-38x.dts. The ethernet@30000 (eth1) is
not used on the AMC board.

This eliminates the following bootup message

  Device 'ethernet@70000': seq 0 is in use by 'ethernet@34000'

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-10 12:36:52 +01:00
Eddie Cai
c3d098e762 rockchip: rk3288: enable rockusb support on rk3288 based device
this patch enable rockusb support on rk3288 based device.

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:06 +01:00
Eddie Cai
1c977772a6 rockchip:usb: add a simple readme for rockusb
add a simple readme to introduce rockusb and tell people how to use it

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:06 +01:00
Eddie Cai
453c95e01a usb: rockchip: add rockusb command
this patch add rockusb command. the usage is
rockusb <USB_controller> <devtype> <dev[:part]>
e.g. rockusb 0 mmc 0

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:06 +01:00
Eddie Cai
bf2b72bef1 usb: rockchip: add the rockusb gadget
this patch implement rockusb protocol on the device side. this is based on
USB download gadget infrastructure. the rockusb function implements the rd,
wl, rid commands. it can work with rkdeveloptool

Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-01-10 11:11:05 +01:00
Chen-Yu Tsai
f4f9896ac3 musb: sunxi: Use base address from device tree
Now that the musb sunxi glue driver is completely device model / device
tree driven, we should use the base address from the device tree,
instead of hard-coding it in the source code.

Fixes: 3a61b080ac ("musb: sunxi: switch to the device model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2018-01-10 11:11:05 +01:00
Tuomas Tynkkynen
34439f73d9 ARM: sunxi: Remove left-over cd-inverted property from pcDuino3
Commit 8620f38409 ("dm: sunxi: Linksprite_pcDuino3: Correct polarity
of MMC card detect") claims that the Pcduino3 device tree had an
incorrect polarity for the card detect pin and thus changed the polarity
flag of the cd-gpios from GPIO_ACTIVE_HIGH to GPIO_ACTIVE_LOW.

Actually the DT was correct since according to the mmc binding, a
combination of GPIO_ACTIVE_HIGH + cd-inverted results in an active-low
polarity. But because the U-Boot driver lacks the code to look at the
cd-inverted property (unlike the Linux driver) it interpreted the
polarity of active-high. Thus, after that commit the DT is actually
wrong from the binding/Linux point of view.

To make both Linux and U-Boot interpret the DT in the same way, just
drop the left-over cd-inverted property. I've sent a Linux patch to
switch all sunxi DTs over to not using the cd-inverted property, so
eventually all sunxi boards in U-Boot will be consistent in not using
cd-inverted.

Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-01-10 11:37:09 +05:30
Maxime Ripard
3afdfd8ddc sunxi: maintainers: Add myself for the TBS A711
Support for that board got introduced recently without the maintainers
part. Let's fix that.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-01-10 11:30:49 +05:30
Chen-Yu Tsai
afe2754412 sunxi: Add support for Libre Computer Board ALL-H3-CC H3 ver.
The Libre Computer Board ALL-H3-CC from Libre Technology is a Raspberry
Pi B+ form factor single board computer based on the Allwinner H3 SoC.
The board has 1GB DDR3 SDRAM, provided by 4 2Gb chips. The mounting holes
and connectors are in the exact same position as on the Raspberry Pi B+.

Raspberry Pi B+ like peripherals supported on this board include:

  - Power input through micro-USB connector (without USB OTG)
  - Native 100 Mbps ethernet using the internal PHY, as opposed to
    USB-based on the RPi
  - 4x USB 2.0 host ports, directly connected to the SoC, as opposed to
    being connected through a USB 2.0 hub on the RPi
  - TV and audio output on a 3.5mm TRRS jack
  - HDMI output
  - Micro-SD card slot
  - Standard RPi B+ GPIO header, with the standard peripherals routed to
    the same pins.

    * 5V, 3.3V power, and ground
    * I2C0 on the H3 is routed to I2C1 pins on the RPi header
    * I2C1 on the H3 is routed to I2C0 pins on the RPi header
    * UART1 on the H3 is routed to UART0 pins on the RPi header
    * SPI0 on the H3 is routed to SPI0 pins on the RPi header,
      with GPIO pin PA17 replacing the missing Chip Select 1
    * I2S1 on the H3 is routed to PCM pins on the RPi header

  - Additional peripherals from the H3 are available on different pins.
    These include I2S0, JTAG, PWM1, SPDIF, SPI1, and UART3

In addition, there are a number of new features:

  - Console UART header
  - Consumer IR receiver
  - Camera interface (not compatible with RPi)
  - Onboard microphone
  - eMMC expansion module port
  - Heatsink mounting holes

This patch adds defconfig and dts files for this board. The dts file is
the same as the one submitted for inclusion in Linux, with some minor
revisions to match the dtsi file and old EMAC bindings in U-boot.

Since the OTG controller is wired to a USB host port, and the H3 has
proper USB hosts to handle host mode, the MUSB driver is not enabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-01-10 11:27:41 +05:30
Siarhei Siamashka
d852600ef0 arm: Exercise v7_arch_cp15_set_acr even without errata fixups
By applying this patch, we are ensuring that the code paths
responsible for applying errata workarounds are also exercised
on CPU revisions, which actually don't need these workarounds.

Only CONFIG_ARM_ERRATA_621766, CONFIG_ARM_ERRATA_454179,
CONFIG_ARM_ERRATA_725233 and CONFIG_ARM_ERRATA_430973 are
covered by this patch (Cortex-A8).

This improves code coverage when testing U-Boot builds
on newer hardware. In particular, the problematic commit
00bbe96eba ("arm: omap: Unify get_device_type() function")
would break both BeageBoard and BeagleBoard XM rather than
just older BeagleBoard.

As an additional bonus, we need fewer instructins and the SPL
size is reduced.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-09 15:31:14 -05:00
Tom Rini
98691a60ab Merge git://git.denx.de/u-boot-rockchip 2018-01-09 13:28:51 -05:00
Miquel Raynal
3f3946d30d pinctrl: mvebu: Make drivers depend on the pinctrl framework
Armada pinctrl drivers shall not be compiled without the entire pinctrl
framework and thus lack a "depends on" condition, otherwise the driver
will simply not be probed.

Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Miquel Raynal
e7ab2ccd15 ARM: mvebu: Allow MVNETA to be selected with Armada 3700 SoCs
Until now, Armada 3700 SoCs could not enable the mvneta driver, and thus
did not benefit from Ethernet support. Add ARMADA_3700 in the
"depends on" list of the MVNETA Kconfig entry.

Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Florian Klink
0f70d705cf arm: mvebu: ClearFog: document boot selection switches, update UART
Signed-off-by: Florian Klink <flokli@flokli.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Andre Heider
6779d65b9f arm64: a37xx: use distro bootcmd
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Andre Heider
e4e18a8acb arm64: a37xx: defconfigs: enable CONFIG_DISTRO_DEFAULTS
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Andre Heider
e1489ba89d arm64: a37xx: add distro compatible env vars
the values of dt_addr_r/kernel_addr_r/ramdisk_addr_r are taken from
the downstream 'u-boot-2017.03-armada-17.10' release.

the chosen values of scriptaddr and pxefile_addr_r are below fdt_addr_r,
in 1MB steps.

Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Andre Heider
d7da570770 arm64: a37xx: use disto defaults
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Konstantin Porotchkin
eee4835d22 tools: Add Marvell recovery image download script
Introduce the recovery image download script for usage with
Marvell Armada SoC families (excepting 37xx family).
Since Marvell BootROM uses a sliding window in UART buffer
for detecting escape sequence during the boot, it's easier
to interrupt the normal boot flow by sending a long stream
of chained escape sequences to the serial port instead of
periodically sending a single escape sequence as it is done
by kwboot utility.
Additional benefit of using this script is the ability to
adjust the escape sequence stream length withoiut need for
compilation.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Igal Liberman <igall@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-09 16:41:00 +01:00
Tom Rini
8c9e6f2817 Merge git://git.denx.de/u-boot-uniphier 2018-01-09 08:45:02 -05:00
Masahiro Yamada
a322eb9ff6 ARM: uniphier: hide memory top by platform hook instead of CONFIG
I do not see a good reason to do this by a CONFIG option that affects
all SoCs.  The ram_size can be adjusted by dram_init() at run-time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-09 21:58:19 +09:00
Masahiro Yamada
3281532ab2 ARM: uniphier: enable CONFIG_MMC_SDHCI_SDMA for ARMv8 SoCs
I did not enable SDMA when I added sdhci-cadence support because LD20
boards are equipped with a large amount memory beyond 32 bit address
range, but SDMA does not support the 64bit address.  U-Boot relocates
itself to the end of effectively available RAM.  This would make the
MMC enumeration fail because the buffer for EXT_CSD allocated in the
stack would go too high, then SDMA would fail to transfer data.

Recent SDHCI-compatible controllers support ADMA, but unfortunately
U-Boot does not support ADMA.

In the previous commit, I hided the DRAM area that exceeds the 32 bit
address range.  Now, I can enable CONFIG_MMC_SDHCI_SDMA.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-09 21:58:18 +09:00
Masahiro Yamada
be893a5c09 ARM: uniphier: do not use RAM that exceeds 32 bit address range
LD20 / PXs3 boards are equipped with a large amount of memory beyond
the 32 bit address range.  U-Boot relocates itself to the end of the
available RAM.

This is a problem for DMA engines that only support 32 bit physical
address, like the SDMA of SDHCI controllers.

In fact, U-Boot does not need to run at the very end of RAM.  It is
rather troublesome for drivers with DMA engines because U-Boot does
not have API like dma_set_mask(), so DMA silently fails, making the
driver debugging difficult.

Hide the memory region that exceeds the 32 bit address range.  It can
be done by simply carving out gd->ram_size.  It would also possible to
override get_effective_memsize() or to define CONFIG_MAX_MEM_MAPPED,
but dram_init() is a good enough place to do this job.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-09 21:58:17 +09:00
Tom Rini
b4b9814f1c arm: socfpga: Guard commands with CONFIG_SPL_BUILD tests
In order for these commands to not be included in SPL we need to guard
compilation with CONFIG_SPL_BUILD checks.  Reorganize some sections of
code slightly in order to avoid new warnings and mark the command
functions as static as they should have been before.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-09 12:38:55 +01:00
Andrey Zhizhikin
08cc52abc9 ARM: socfpga: Enable part command for socfpga platform
Enable CONFIG_CMD_PART item, as default environment requires it
and complains this command in unknown.

Signed-off-by: Andrey Zhizhikin <andrey.z@gmail.com>
2018-01-09 12:38:55 +01:00
Ran Wang
91f4fb9b89 arm64: layerscape: Move CONFIG_HAS_FSL_DR_USB to Kconfig
Rename to USB_EHCI_FSL, use Kconfig to select ehci accordingly.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2018-01-09 12:37:15 +01:00
Ran Wang
be3872ea81 usb: ehci: fsl: Fix some compile warnings.
When enable CONFIG_HAS_FSL_DR_USB, we might encounter below compile
warning, apply this patch can fix it:

drivers/usb/host/ehci-fsl.c:109:4: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
   ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
    ^
drivers/usb/host/ehci-fsl.c:108:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  hcor = (struct ehci_hcor *)
         ^
drivers/usb/host/ehci-fsl.c:115:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        (u32)hccr, (u32)hcor,
        ^
include/log.h:131:26: note: in definition of macro 'debug_cond'
    printf(pr_fmt(fmt), ##args); \
                          ^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
  debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
  ^~~~~
drivers/usb/host/ehci-fsl.c:115:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
        (u32)hccr, (u32)hcor,
                   ^
include/log.h:131:26: note: in definition of macro 'debug_cond'
    printf(pr_fmt(fmt), ##args); \
                          ^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
  debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
  ^~~~~

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2018-01-09 12:37:15 +01:00
Ran Wang
8d9c3c2253 armv8: ls1012a: Add USB 2.0 controller phy type for ls1012aqds board
Without this propertiy, U-Boot will pop warning of 'USB phy type not
defined' when select CONFIG_HAS_FSL_DR_USB.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2018-01-09 12:37:15 +01:00
Elaine Zhang
538f67c332 rockchip: clk: bind reset driver
Bind rockchip reset to clock-controller with rockchip_reset_bind().

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-09 11:13:32 +01:00
Elaine Zhang
760188c1aa rockchip: reset: support a (common) rockchip reset drivers
Create driver to support the soft reset (i.e. peripheral)
of all Rockchip SoCs.

Example of usage:
i2c driver:
	ret = reset_get_by_name(dev, "i2c", &reset_ctl);
	if (ret) {
		error("reset_get_by_name() failed: %d\n", ret);
	}

	reset_assert(&reset_ctl);
	udelay(50);
	reset_deassert(&reset_ctl);

i2c dts node:
resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
reset-names = "p_i2c", "i2c";

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed commit tag:]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-01-09 11:13:32 +01:00
Tom Rini
f3dd87e0b9 Prepare v2018.01
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-08 20:25:29 -05:00
Tom Rini
2f4c9de3d0 Merge git://git.denx.de/u-boot-imx 2018-01-08 12:51:47 -05:00
Jagan Teki
ca9d211e2c mtd: nand: mxs_nand_spl: Remove nand size print
It is not much needed to print nand size in SPL during nand boot,
and most of nand spl drivers doesn't print the same.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-01-08 17:37:12 +01:00
Jagan Teki
ff8822998f board: engicam: Fix to remove legacy board/icorem6_rqs
board/icorem6_rqs/ is forgot to remove while moving
common board files together in
(sha1: 52aaddd6f4)
"i..MX6: engicam: Add imx6q/imx6ul boards for existing boards"

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-01-08 17:36:54 +01:00
Stefan Agner
46718353b2 imx: initialize and use generic timer on i.MX 6UL/ULL
The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM
generic timer. This change makes use of the ARM generic timer in
U-Boot.

This is crucial to make the ARM generic timers usable in Linux since
timer_init() initalizes the system counter module, which is necessary
to use the generic timers CP15 registers.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-08 17:33:06 +01:00
Stefan Agner
23b6a131fd imx: introduce CONFIG_GPT_TIMER
Introduce a new config symbol to select the i.MX
General Purpose Timer (GPT).

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-08 17:33:06 +01:00
Stefan Agner
616aa55d17 imx: move CONFIG_SYSCOUNTER_TIMER to Kconfig
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-08 17:33:06 +01:00
Tom Rini
5e2338079d Merge git://git.denx.de/u-boot-x86 2018-01-08 08:26:46 -05:00
Clemens Gruber
598e9dccc7 crypto/fsl: fix BLOB encapsulation and decapsulation
The blob_encap and blob_decap functions were not flushing the dcache
before passing data to CAAM/DMA and not invalidating the dcache when
getting data back.
Therefore, blob encapsulation and decapsulation failed with errors like
the following due to data cache incoherency:
"40000006: DECO: desc idx 0: Invalid KEY command"

To ensure coherency, we require the key_mod, src and dst buffers to be
aligned to the cache line size and flush/invalidate the memory regions.
The same requirements apply to the job descriptor.

Tested on an i.MX6Q board.

Reviewed-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2018-01-08 08:26:03 -05:00