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https://github.com/AsahiLinux/u-boot
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board: stm32f429-discovery: switch to DM STM32 sdram driver
Use available DM stm32_sdram.c driver instead of board SDRAM initialization. For that, enable OF_CONTROL, OF_EMBED and STM32_SDRAM flags. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
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791651e390
commit
7fd65ef552
3 changed files with 20 additions and 125 deletions
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@ -15,10 +15,8 @@
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#include <dm.h>
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#include <stm32_rcc.h>
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#include <asm/io.h>
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#include <asm/armv7m.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/fmc.h>
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#include <dm/platform_data/serial_stm32.h>
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#include <asm/arch/stm32_periph.h>
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#include <asm/arch/stm32_defs.h>
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@ -140,56 +138,10 @@ out:
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*/
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#define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
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static inline u32 _ns2clk(u32 ns, u32 freq)
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{
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u32 tmp = freq/1000000;
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return (tmp * ns) / 1000;
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}
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#define NS2CLK(ns) (_ns2clk(ns, freq))
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/*
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* Following are timings for IS42S16400J, from corresponding datasheet
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*/
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#define SDRAM_CAS 3 /* 3 cycles */
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#define SDRAM_NB 1 /* Number of banks */
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#define SDRAM_MWID 1 /* 16 bit memory */
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#define SDRAM_NR 0x1 /* 12-bit row */
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#define SDRAM_NC 0x0 /* 8-bit col */
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#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
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#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
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#define SDRAM_TRRD (NS2CLK(14) - 1)
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#define SDRAM_TRCD (NS2CLK(15) - 1)
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#define SDRAM_TRP (NS2CLK(15) - 1)
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#define SDRAM_TRAS (NS2CLK(42) - 1)
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#define SDRAM_TRC (NS2CLK(63) - 1)
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#define SDRAM_TRFC (NS2CLK(63) - 1)
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#define SDRAM_TCDL (1 - 1)
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#define SDRAM_TRDL (2 - 1)
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#define SDRAM_TBDL (1 - 1)
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#define SDRAM_TREF 1386
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#define SDRAM_TCCD (1 - 1)
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#define SDRAM_TXSR (NS2CLK(70) - 1)/* Row cycle time after precharge */
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#define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */
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/* Last data-in to row precharge, need also comply ineq from RM 37.7.5 */
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#define SDRAM_TWR max(\
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(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD - 1)), \
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(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP - 2)\
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)
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#define SDRAM_MODE_BL_SHIFT 0
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#define SDRAM_MODE_CAS_SHIFT 4
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#define SDRAM_MODE_BL 0
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#define SDRAM_MODE_CAS SDRAM_CAS
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int dram_init(void)
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{
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u32 freq;
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int rv;
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struct udevice *dev;
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rv = fmc_setup_gpio();
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if (rv)
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@ -197,85 +149,25 @@ int dram_init(void)
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setbits_le32(&STM32_RCC->ahb3enr, STM32_RCC_ENR_FMC);
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/*
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* Get frequency for NS2CLK calculation.
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*/
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freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
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rv = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (rv) {
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debug("DRAM init failed: %d\n", rv);
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return rv;
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}
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writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
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| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
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| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
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&STM32_SDRAM_FMC->sdcr1);
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writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
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| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
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| SDRAM_NB << FMC_SDCR_NB_SHIFT
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| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
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| SDRAM_NR << FMC_SDCR_NR_SHIFT
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| SDRAM_NC << FMC_SDCR_NC_SHIFT
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| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
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| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
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&STM32_SDRAM_FMC->sdcr2);
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writel(SDRAM_TRP << FMC_SDTR_TRP_SHIFT
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| SDRAM_TRC << FMC_SDTR_TRC_SHIFT,
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&STM32_SDRAM_FMC->sdtr1);
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writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
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| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
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| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
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| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
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| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
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| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
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| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
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&STM32_SDRAM_FMC->sdtr2);
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writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_START_CLOCK,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(200); /* 200 us delay, page 10, "Power-Up" */
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_PRECHARGE,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel((FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_AUTOREFRESH
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| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_2 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
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| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
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<< FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
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&STM32_SDRAM_FMC->sdcmr);
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udelay(100);
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FMC_BUSY_WAIT();
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writel(FMC_SDCMR_BANK_2 | FMC_SDCMR_MODE_NORMAL,
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&STM32_SDRAM_FMC->sdcmr);
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FMC_BUSY_WAIT();
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/* Refresh timer */
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writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
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/*
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* Fill in global info with description of SRAM configuration
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
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gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
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gd->ram_size = CONFIG_SYS_RAM_SIZE;
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if (fdtdec_setup_memory_size() != 0)
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rv = -EINVAL;
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return rv;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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static const struct stm32_serial_platdata serial_platdata = {
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.base = (struct stm32_usart *)STM32_USART1_BASE,
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};
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@ -2,6 +2,7 @@ CONFIG_ARM=y
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CONFIG_STM32=y
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CONFIG_STM32F4=y
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CONFIG_TARGET_STM32F429_DISCOVERY=y
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CONFIG_DEFAULT_DEVICE_TREE="stm32f429-disco"
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
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CONFIG_CMD_IMLS=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TIMER=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_EMBED=y
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CONFIG_ENV_IS_IN_FLASH=y
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# CONFIG_MMC is not set
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_OF_LIBFDT=y
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CONFIG_RAM=y
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CONFIG_STM32_SDRAM=y
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* Configuration of the external SDRAM memory
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_RAM_SIZE (8 << 20)
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#define CONFIG_SYS_RAM_CS 1
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#define CONFIG_SYS_RAM_FREQ_DIV 2
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#define CONFIG_SYS_RAM_BASE 0xD0000000
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