Commit graph

57310 commits

Author SHA1 Message Date
James Byrne
77b508d34b net: phy: micrel: Allow KSZ8xxx and KSZ90x1 to be used together
Commit d397f7c45b ("net: phy: micrel: Separate KSZ9000 drivers from
KSZ8000 drivers") separated the KSZ8xxx and KSZ90x1 drivers and warns
that you shouldn't select both of them due to a device ID clash between
the KSZ9021 and the KS8721, asserting that "it is highly unlikely for a
system to contain both a KSZ8000 and a KSZ9000 PHY". Unfortunately
boards like the SAMA5D3xEK do contain both types of PHY, but fortunately
the Linux Micrel PHY driver provides a solution by using different PHY
ID and mask values to distinguish these chips.

This commit contains the following changes:

- The PHY ID and mask values for the KSZ9021 and the KS8721 now match
those used by the Linux driver.
- The warnings about not enabling both drivers have been removed.
- The description for PHY_MICREL_KSZ8XXX has been corrected (these are
10/100 PHYs, not GbE PHYs).
- PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 no longer select PHY_GIGE
since this is selected by PHY_MICREL_KSZ90X1.
- All of the relevant defconfig files have been updated now that
PHY_MICREL_KSZ8XXX does not default to 'Y'.

Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-14 14:43:33 -05:00
Marek Vasut
9e6ed1a346 ARM: dts: socfpga: Keep FPGA bridge entries in SPL DT
Keep the FPGA bridge entries in SPL DT to let do_bridge_reset() toggle
the bridges on/off as needed according to the handoff file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-14 19:53:16 +02:00
Marek Vasut
917bd8a876 ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff files
Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT files to make it obvious what gets included where without
having to follow confusing long chain of includes, i.e. board DT file includes
everything it needs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-14 19:53:16 +02:00
Wolfgang Grandegger
990ed4452c arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK and MCVEVP baseboard. The board can boot
from eMMC. Ethernet and USB is supported.

The Aries Embedded boards have been removed with commit 03b54997d5
("board/aries: Remove"). I will now take care of them.

The device-tree files are from mainline Linux commit e93c9c99a629
("Linux v5.1)".

Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
CC: Marek Vasut <marex@denx.de>
CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-14 19:52:39 +02:00
Simon Goldschmidt
48ec73453a arm: sofcpga: s10: remove unused ad-hoc reset code
The stratix 10 reset manager ad-hoc code in arch/arm contains an unused
function 'reset_deassert_peripherals_handoff' that has been added from
the beginning. As this is probably a result of copying the gen5 reset
manager and this function has never been used, remove it.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-14 19:52:39 +02:00
Simon Goldschmidt
430b42f76a arm: socfpga: remove re-added ad-hoc reset code
commit c5de2b7eae ("arm: socfpga: implement proper peripheral reset")
has removed the call to 'reset_deassert_peripherals_handoff()' from
socfpga gen5 SPL since the reset driver now handles resets. However,
commit c1d4b464c8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
has re-added this ad-hoc reset code, so that all peripherals were now
again enabled instead of letting the drivers enable them by request.

While at it, remove this function for gen5 as it should not be used.

Fixes: commit c1d4b464c8 ("ARM: socfpga: Disable bridges in SPL unless booting from FPGA")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-14 19:52:38 +02:00
Marek Vasut
851224460f ARM: renesas: grpeach: Align env position
Move the U-Boot environment to 0x80000 to match the downstream
vendor fork and allow easy migration from one to the other.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-14 19:52:04 +02:00
Tom Rini
90176e3be6 Pull request for UEFI sub-system for v2019.07-rc3
The development target for the UEFI sub-system is EBBR compliance. We have
 already implemented some further protocols to enable running the UEFI Shell
 and the UEFI SCT test suite.
 
 As some boards are severely memory constrained make some of these extras
 customizable.
 
 Provide bug fixes. The most prominent ones let us pass the UEFI SCT memory
 allocation tests.
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Merge tag 'efi-2019-07-rc3' of git://git.denx.de/u-boot-efi

Pull request for UEFI sub-system for v2019.07-rc3

The development target for the UEFI sub-system is EBBR compliance. We have
already implemented some further protocols to enable running the UEFI Shell
and the UEFI SCT test suite.

As some boards are severely memory constrained make some of these extras
customizable.

Provide bug fixes. The most prominent ones let us pass the UEFI SCT memory
allocation tests.
2019-05-13 07:13:28 -04:00
Tom Rini
d2d8f73da4 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- A10 FPGA programming support, Gen5 livetree conversion
2019-05-13 07:13:03 -04:00
Tom Rini
592254b9b8 Merge branch 'master' of git://git.denx.de/u-boot-sh
- SH2, SH3 removal
2019-05-13 07:12:47 -04:00
Heinrich Schuchardt
e2d82f8b2a efi_loader: comments for efi_install_fdt()
Describe that efi_install_fdt() defaults to using the device tree
indicated by environment variable fdtcontroladdr.

ACPI tables and device trees are mutually exclusive.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:23 +02:00
Heinrich Schuchardt
7e92db810b efi_loader: deduplicate code in cmd/bootefi.c
Move duplicate initialization code to single instance.

Adjust comments of concerned functions.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:23 +02:00
Heinrich Schuchardt
05fefe7681 efi_loader: ACPI device node to text
The device path to text protocol renders ACPI device nodes incorrectly.

Use capital hexadecimal numbers as shown in the UEFI spec examples.

Always output the optional UID. This matches what UEFI SCT expects and
saves us an `if`.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
3b985113be efi_loader: infinite recursion notifying events
UEFI SCT uses this call sequence to determine the current TPL level inside
notification functions:

    OldTpl = BS->RaiseTPL(TPL_HIGH_LEVEL);
    BS->RestoreTPL(OldTpl);

In RestoreTPL() we trigger the notification function of queued events. If
we do not mark the event as non-queued before calling the notification
function, this results in an infinite recursive call sequence.

Mark the event as non-queued before entering the notification function.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
8ae39857b9 efi_loader: simplify efi_allocate_pages()
Replace unnecessary control structures by using return statements.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
f756fe83b0 efi_loader: AllocateAdress error handling
If AllocatePages() is called with AllocateAddress, the UEFI spec requires
to return EFI_NOT_FOUND in case the memory page does not exist.

The UEFI SCT II 2017 spec additionally requires to return EFI_NOT_FOUND if
the page is already allocated.

Check that *Memory refers to an unallocated page.

UEFI SCT II (2017): AllocatePages(), 5.1.2.1.9 - 5.1.2.1.10

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
735fd22800 efi_loader: out of resources in AllocatePages()
According to the UEFI AllocatePages() has to return EFI_OUT_OF_RESOURCES if
sufficient memory is not available.

Change the return value.

UEFI SCT II (2017): 3.2.1 AllocatePages(), 5.1.2.1.8

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
7d3af58ed9 efi_loader: check memory address before freeing
When we call FreePages() we essentially add memory to our memory map. We
shouldn't do this for memory that does not exit.

Check if the memory that is to be freed via FreePages() or FreePool() is in
our memory map and is not EFI_CONVENTIONAL_MEMORY.

This check is mandated by the UEFI specification.

Cf. UEFI SCT  II (2017), 3.2.2 FreePages(), 5.1.2.1 - 5.1.2.2

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
96aa99cded efi_loader: error code in UninstallProtocolInterface()
According to the UEFI specification UninstallProtocolInteface() has to
return EFI_NOT_FOUND if the interface is not found.

Correct the return value.

Cf. UEFI SCT II spec (2017), 3.3.2 UninstallProtocolInterface(), 5.1.3.2.4

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
61c63db7fe efi_loader: superfluous check in efi_remove_protocol()
efi_search_protocol() already checks that the GUID matches. Don't check
a second time.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
ab557141c2 efi_loader: LocateDevicePath() incorrect parameter check
A parameter check in LocateDevicePath() does not match the requirements of
the UEFI spec.

If device is NULL, only return EFI_INVALID_PARAMETER if a matching handle
is found.

Cf. UEFI SCT II specification (2017)3.3.7 LocateDevicePath(), 5.1.3.7.3

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
0a84319665 efi_loader: fix typo in efi_locate_handle() comment
%s/not buffer/no buffer/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
64b5ba4d29 efi_loader: make device path to text protocol customizable
The device path to text protocol is not needed for EBBR compliance. So
let's make it a customizable option.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
334997356e efi_loader: make Unicode collation protocol customizable
The Unicode collation protocol is not needed for EBBR compliance. So let's
make it a customizable option.

The Unicode capitalization table is only needed by this protocol. So let it
depend on the Unicode collation protocol.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
9363fd22df efi_loader: reword the EFI_LOADER config option
No need to mention U-Boot in brief description.
Fix several typos, mention iPXE.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
5684c8d1ea efi_loader: format Kconfig
Use if/endif for dependencies to give structure to the configuration menu.

Sort important settings to the top.

Abbreviate the short description of EFI_LOADER_HII.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
5ad3877448 efi_loader: observe CONFIG_EFI_LOADER_HII
If EFI_LOADER_HII is not set, do not unnecessarily compile files for HII
protocols.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
1db6ab28b2 MAINTAINERS: assign include/charset.h
Assign include/charset.h to EFI PAYLOAD.

The functions defined in this include are used by the UEFI sub-system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:22 +02:00
Heinrich Schuchardt
8a4c443c00 lib: charset: correct utf8_utf16_strnlen() description
Correct the description of utf8_utf16_strnlen() and utf8_utf16_strlen() to
reflect that they return u16 count and not byte count.

For these functions and utf16_utf8_strnlen() describe the handling of
invalid code sequences.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-05-12 20:54:21 +02:00
Simon Goldschmidt
1b898ffc04 gpio: dwapb_gpio: convert to livetree
Convert 'gpio_dwapb_bind' to iterate over subnodes using livetree
functions (inspired from mt7621_gpio.c).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10 22:48:11 +02:00
Simon Goldschmidt
6cdd0a4e54 reset: socfpga: convert to livetree
Convert 'socfpga_reset_probe' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int'.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10 22:48:11 +02:00
Simon Goldschmidt
41b22c0acc serial: altera_uart: convert to livetree
Convert 'altera_uart_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10 22:48:11 +02:00
Simon Goldschmidt
27c3e07bcb spi: designware: convert to livetree
Convert 'dw_spi_ofdata_to_platdata' to use 'dev_read_u32_default'
instead of 'fdtdec_get_int' and get rid of DECLARE_GLOBAL_DATA_PTR.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10 22:48:11 +02:00
Simon Goldschmidt
46b633d7b4 spi: cadence_qspi: convert to livetree
Convert 'cadence_spi_ofdata_to_platdata' to use dev_read_* functions to
read driver parameters and 'dev_read_first_subnode'/'ofnode_read_*' to
read flash (child node) parameters.

Tested on socfpga_socrates (socfpga gen5).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10 22:48:11 +02:00
Simon Goldschmidt
460a97f3a2 timer: dw-apb: remove unused DECLARE_GLOBAL_DATA_PTR
The dw-apb timer does not use 'gd', so remove its declaration.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-10 22:48:11 +02:00
Ley Foon Tan
8ede7515fe configs: stratix10: Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
Fix SPI flash environment erase size error.

CONFIG_ENV_SECT_SIZE is set to 4KB. Enable CONFIG_SPI_FLASH_USE_4K_SECTORS
to allow erase one environment sector.

Fix error below:

SOCFPGA_STRATIX10 # saveenv
Saving Environment to SPI Flash...
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Erasing SPI flash...SF: Erase offset/length not multiple of erase size
Failed (-22)

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-10 22:48:11 +02:00
Tien Fong Chee
da0d5f6f73 ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
Increasing Malloc pool size up to 0x15000 is required to support FAT in SPL
. The result of calculation is come from default max cluster(0x10000) +
others(0x2000) + additional memory for headroom(0x3000).

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:11 +02:00
Tien Fong Chee
1a0d0b7841 ARM: socfpga: Synchronize the configuration for A10 SoCDK
Update the default configuration file to enable the necessary functionality
the get the kit working.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:11 +02:00
Tien Fong Chee
1085bb3cba spl: socfpga: Implement fpga bitstream loading with socfpga loadfs
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:11 +02:00
Tien Fong Chee
f61d529260 ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
Update the default configuration file to enable the necessary functionality
to get the SoCFPGA loadfs driver support. This would enable the
implementation of programming bitstream into FPGA from MMC.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:11 +02:00
Tien Fong Chee
0a42a132a4 ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:11 +02:00
Tien Fong Chee
c1cf539180 ARM: socfpga: Moving the watchdog reset to the for-loop status polling
Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:10 +02:00
Tien Fong Chee
f4b53b24d0 ARM: socfpga: Cleaning up and ensuring consistent format messages in driver
Ensure all the debug messages are always prefix with "FPGA: " and comment
beginning with uppercase letter.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:10 +02:00
Tien Fong Chee
f78b505f81 ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
Add default fitImage file bundling FPGA bitstreams for Arria10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:10 +02:00
Tien Fong Chee
5c2ae96b60 ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10
This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:10 +02:00
Marek Vasut
d0487da83f sh: sh3: Remove CPU support
This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-05-10 22:43:18 +02:00
Marek Vasut
89a6b74636 sh: shmin: Remove the board
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-05-10 22:43:18 +02:00
Marek Vasut
d7d7e84856 sh: ms7720se: Remove the board
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-05-10 22:43:18 +02:00
Marek Vasut
a786d9be88 sh: mpr2: Remove the board
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Mark Jonas <mark.jonas@de.bosch.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-05-10 22:43:18 +02:00
Marek Vasut
7de3ea8b98 sh: sh2: Remove CPU support
This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
2019-05-10 22:43:18 +02:00