Commit graph

39456 commits

Author SHA1 Message Date
Paul Burton
3f96f87520 clk: Use dummy clk_get_by_* functions when CONFIG_CLK is disabled
The implementations of clk_get_by_index & clk_get_by_name are only
available when CONFIG_CLK is enabled. Provide the dummies when this is
not the case in order to avoid build failures.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-21 15:04:32 +02:00
Paul Burton
639200f6a0 MIPS: Ensure cache ops complete in mips_cache_reset
Ensure that cache operations complete before returning from
mips_cache_reset by placing a completion barrier (sync instruction)
before the return. Without this there is no guarantee that the cache ops
will complete before any subsequent memory accesses, since they are
indexed cache ops & thus not implicitly ordered with memory accesses.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
d608254b0a MIPS: Clear hazard between TagLo writes & cache ops
Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
c5b8412d60 MIPS: Ensure Config.K0=2 applies before any memory accesses
During boot we set Config.K0=2 (uncached) such that any accesses to the
kseg0 memory region are performed uncached before the caches are
initialised. This write to the Config register introduces an execution
hazard between it & any following memory accesses (such as the load of
_gp), which we need to clear in order to ensure those memory accesses
are actually performed uncached. Clear this execution hazard with the
insertion of an ehb execution hazard barrier instruction.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
566ce04de4 MIPS: Malta: Enable CM & L2 support
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
7953354b07 MIPS: Join the coherent domain when a CM is present
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
4baa0ab67d MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.

If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
b2b135d980 MIPS: Map CM Global Control Registers
Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
5c72e5a62e MIPS: Define register names for cache init
Define names for registers holding cache sizes throughout
mips_cache_reset, in order to make the code easier to read & allow for
changing register assignments more easily.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
f8981277f5 MIPS: If we don't need DDR for cache init, init cache first
On systems where cache initialisation doesn't require zeroed memory (ie.
systems where CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD is not defined)
perform cache initialisation prior to lowlevel_init & DDR
initialisation. This allows for DDR initialisation code to run cached &
thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
4f9226b403 MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
33b5c9b209 MIPS: Enable use of the instruction cache earlier
Enable use of the instruction cache immediately after it has been
initialised. This will only take effect if U-Boot was linked to run from
kseg0 rather than kseg1, but when this is the case the data cache
initialisation code will run cached & thus significantly faster.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
8cb4817d0f MIPS: Probe cache line sizes once during boot
Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot & store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more important once L2 caches which may expose their properties
via coprocessor 2 or the CM are supported.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
0dfe04d6c8 MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init
In order to prepare for MIPS arch code making use of arch_cpu_init in a
later patch, stop using it from ath79 SoC code & instead use the new
mach_cpu_init which is provided for this purpose.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
8ebf50692e board_f: Add a mach_cpu_init callback
Currently we have a mismash of architectures which use arch_cpu_init
from architecture-wide code (arc, avr32, blackfin, mips, nios2, xtensa)
and architectures which use arch_cpu_init from machine/SoC level code
(arm, x86).

In order to clean this mess up & allow for both use cases, introduce a
new mach_cpu_init callback which is run immediately after arch_cpu_init.
This will allow for architectures to have arch-wide code without needing
individual machines to all implement their own arch_cpu_init with a call
to some common function.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-21 15:04:04 +02:00
Zubair Lutfullah Kakakhel
ebf2b9e3df mips: Add MIPSfpga platform support
MIPSfpga is an FPGA based dev platform.

In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks

The FPGA dev board used is the Nexys4DDR board by Digilent.

For more information, check the Readme file in board/imgtec/xilfpga

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-21 14:55:14 +02:00
Zubair Lutfullah Kakakhel
d4e85377e7 mips: xilfpga: Add device tree files
Mostly the same as the Kernel upstream device tree file except for

- alias for the serial console node
- ethernet node as the ethernet stuff isn't upstream on kernel.org yet
- uart clock-frequency passed directly in the node

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-09-21 14:55:14 +02:00
Zubair Lutfullah Kakakhel
2f1f05f432 net: emaclite: Enable driver for MIPS
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-21 14:55:14 +02:00
Zubair Lutfullah Kakakhel
611fe0bddb net: emaclite: use __raw_readl/writel instead of weird define
out_be32 and in_be32 are actually #defined to little endian
writel/readl in arch/microblaze.

Just use __raw_writel/readl instead. That is also what is used
in the Linux kernel driver for this IP block

Tested on MIPSfpga. Can tftp a kernel.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-21 14:55:14 +02:00
Zubair Lutfullah Kakakhel
39e020ef16 net: emaclite: Use ioremap_nocache
Virtual to physical mapping isn't necessarily 1:1 for all architectures

Using ioremap_nocache allows for the arch code to translate the
physical address to a virtual address.

Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-09-21 14:55:14 +02:00
Masahiro Yamada
9b1b6d4225 Revert "Increase default of CONFIG_SYS_MALLOC_F_LEN for SPL_OF_CONTROL"
This reverts commit 90c08d9e08.

I took a closer look at this after the commit was applied, and found
CONFIG_SYS_MALLOC_F_LEN=0x2000 was too much.  8KB memory for SPL is
actually too big for some boards.  Perhaps 0x800 is enough, but the
situation varies board by board.

Let's postpone our decision until we come up with a better idea.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-19 15:20:09 -04:00
Tom Rini
00709f5697 A20-OLinuXino-Lime2: Enable USB gadget support
Based on A13-OLinuXino, enable DFU and UMS support.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
2016-09-19 11:37:06 -04:00
Tom Rini
9a6535e05f Merge branch 'master' of git://git.denx.de/u-boot-uniphier 2016-09-18 14:05:30 -04:00
Tom Rini
b58d351244 Merge branch 'master' of git://www.denx.de/git/u-boot-sunxi 2016-09-18 14:05:29 -04:00
Tom Rini
a7a97fddb3 Merge branch 'master' of git://www.denx.de/git/u-boot-arc 2016-09-18 14:05:28 -04:00
Masahiro Yamada
f9d7e17e84 ARM: uniphier: update DRAM init code for LD20 SoC
Import the latest version from the Diag software.

  - Support LD21 SoC (including DDR chips in the package)
  - Per-board granule adjustment for both reference and TV boards
  - Misc cleanups

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:12:26 +09:00
Masahiro Yamada
682e09ff9f ARM: uniphier: add PLL init code for LD20 SoC
Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper.  Split the common code into pll-base-ld20.c for easier
re-use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:12:26 +09:00
Masahiro Yamada
fcc238baee ARM: uniphier: collect clock/PLL init code into a single directory
Now PLLs for DRAM controller are initialized in SPL, and the others
in U-Boot proper.  Setting up all of them in a single directory will
be helpful when we want to share code between SPL and U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:06:47 +09:00
Masahiro Yamada
6a3e4274e4 ARM: uniphier: move PLL init code to U-Boot proper where possible
The PLL for the DRAM interface must be initialized in SPL, but the
others can be delayed until U-Boot proper.  Move them from SPL to
U-Boot proper to save the precious SPL memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-19 00:06:44 +09:00
Masahiro Yamada
22de6b3374 ARM: uniphier: rename CONFIG_DPLL_SSC_RATE_1PER
Basically, this should not be configured by users.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:47:27 +09:00
Masahiro Yamada
b78ffc53c5 ARM: uniphier: move XIRQ pin-mux settings of LD11/LD20
This is the last code in the mach-uniphier/pinctrl/ directory.
Push the remaining code out to delete the directory entirely.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:47:27 +09:00
Masahiro Yamada
68557ec37e ARM: uniphier: consolidate System Bus pin-mux settings for LD11/LD20
Use the pin-mux data in the pinctrl drivers by directly calling
pinctrl_generic_set_state().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:47:18 +09:00
Masahiro Yamada
6bf12eaea4 ARM: dts: uniphier: include System Bus pin group node in SPL DT
This will be needed for setting up the System Bus pin-mux via the
LD11/LD20 pinctrl driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:46 +09:00
Masahiro Yamada
5ac9dfbe9d ARM: uniphier: consolidate NAND pin-mux settings
The NAND subsystem has not supported the Driver Model yet, but the
NAND pin-mux data are already in the pinctrl drivers.  Use them by
calling pinctrl_generic_set_state() directly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:44 +09:00
Masahiro Yamada
6a93478b93 ARM: uniphier: remove ad-hoc pin-mux code for sLD3
These settings are nicely cared by the pinctrl driver now.  Remove.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:37 +09:00
Masahiro Yamada
cd477c9def ARM: uniphier: remove redundant pin-muxing for EA24 pin of sLD3 SoC
This is enabled by default for all the supported boot modes.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:36 +09:00
Masahiro Yamada
27350c922e ARM: uniphier: select PINCTRL and SPL_PINCTRL
Now all UniPhier SoCs support a pinctrl driver.  Select (SPL_)PINCTRL
since it is mandatory even for base use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:35 +09:00
Masahiro Yamada
4475c0ca5f ARM: dts: uniphier: add pinctrl device node and pinctrl properties
DT-side updates to make pinctrl on sLD3 SoC really available.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:29 +09:00
Masahiro Yamada
24572db909 pinctrl: uniphier: add UniPhier sLD3 pinctrl driver
Add pin-mux support for UniPhier sLD3 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:17 +09:00
Masahiro Yamada
bbb119800f pinctrl: uniphier: support 4bit-width pin-mux register capability
On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit
wide on sLD3 SoC.  Support it for the sLD3 pinctrl driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-18 23:10:11 +09:00
Chen-Yu Tsai
ca7628a911 sunxi: Enable USB gadget support for Sinlinx SinA33
Sinlinx SinA33 has a USB OTG port, but VBUS is controlled manually from
a jumper pad.

Enable OTG in gadget mode, as well as the download gadget and related
functions.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18 14:39:16 +02:00
Chen-Yu Tsai
28de49be57 sunxi: Enable USB host support for Sinlinx SinA33
Sinlinx SinA33 has 1 USB host port. Enable EHCI_HCD support for it.
Also enable USB mass storage support so we can access USB sticks.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18 14:39:16 +02:00
Chen-Yu Tsai
01cf4a1af2 sunxi: Add mmc0 card detect pin for Sinlinx SinA33
Sinlinx SinA33 uses PB4 for mmc0 card detect.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18 14:39:16 +02:00
Jelle van der Waa
348df5b92c sunxi: Add defconfig and dts for the NanoPi NEO
The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb
and one usb OTG connector.

Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18 14:39:16 +02:00
Hans de Goede
7c22e26ec5 sunxi: musb: Re-init musb controller on repeated probe calls
With sunxi-musb musb_lowlevel_init() can fail when a charger; or no cable
is plugged into the otg port.

To avoid leaking the struct musb allocated by musb_init_controller()
on repeated musb_usb_probe() calls, we were caching its result.
But musb_init_controller() does more, such as calling sunxi_musb_init()
which enables the clocks.

Not calling sunxi_musb_init() causes the musb controller to stop working
after a "usb reset" since that calls musb_usb_remove() which disables the
clocks.

This commit fixes this by removing the caching of the struct returned
from musb_init_controller(), it replaces this by free-ing the allocated
memory in musb_usb_remove() and calling musb_usb_remove() on
musb_usb_probe() errors to ensure proper cleanup.

While at it also make musb_usb_probe() and musb_usb_remove() static.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-18 14:39:16 +02:00
Chen-Yu Tsai
57075a472a sunxi: musb: Power off OTG port VBUS when disabled
The Linux kernel musb driver expects VBUS to be off while initializing
musb. Having it on results in a repeating string of warnings, followed
by an unusable peripheral. The peripheral is only usable after
physically removing the OTG adapter, letting musb reset its state.

This partially reverts commit c9f8947e66 ("sunxi: usb-phy: Never
power off the usb ports")

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-09-17 14:37:40 +02:00
Hans de Goede
253e62bf4b sunxi: axp2xx: disable ldoio0/1 at boot
When cold-booting the ldoio0/1 regulators are always off / the
gpios are always at tristate. But when re-booting from android these
are sometimes on. Disable them at axp_init time (iow as early as possible)
to remove this difference between a cold boot and a reboot.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-09-17 14:37:39 +02:00
Simon Glass
371244cb19 Makefile: Give a build error if ad-hoc CONFIG options are added
New CONFIG options should be added via Kconfig. To help prevent new ad-hoc
CONFIGs from being added, give a build error when these are detected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2016-09-16 17:27:24 -04:00
Simon Glass
eed921d923 Kconfig: Add a whitelist of ad-hoc CONFIG options
Add a list of ad-hoc CONFIG options that don't use Kconfig. This can be used
to check that new ones are not being added.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:24 -04:00
Simon Glass
696a91f2b0 Convert CONFIG_SPL_YMODEM_SUPPORT to Kconfig
Convert CONFIG_SPL_YMODEM_SUPPORT to Kconfig

Move this option to Kconfig and tidy up existing uses.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-16 17:27:23 -04:00