Add support for DEBUG_UART on ARC devboards
This required us to do 2 things:
1) Insert a call to debug_uart_init() in early boot code
2) Convert serial_arc to Kconfig
Once both items above are done we just patched defconfigs.
Some minor fixes for the Raspberry Pi:
- Fix SD writes on new sdhost controller
- Sanitize default load addresses, allowing for better payload placement
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Merge tag 'signed-rpi-next' of git://github.com/agraf/u-boot
Patch queue for rpi - 2018-05-24
Some minor fixes for the Raspberry Pi:
- Fix SD writes on new sdhost controller
- Sanitize default load addresses, allowing for better payload placement
Last user of this driver went away in May 2017 in commit
eb5ba3aefd ("i2c: Drop use of CONFIG_I2C_HARD").
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Heiko Schocher <hs@denx.de>
Last user of this driver went away in June 2015 in commit
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: Heiko Schocher <hs@denx.de>
Last user of this driver went away in June 2015 in commit
d928664f41 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
dm_warn is too noisy, replace with dev_dbg for less noise.
Based on original work by Wenyou Yang
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Convert CONFIG_SUPPORT_EMMC_RPMB to Kconfig. Split the command handling
from the underlying support and expose this through CMD_MMC_RPMB.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
The bcm2835 sdhost driver has a problem with "write multiple" commands.
It seems to boil down to the fact that the controller dislikes its FIFO
to get drained at the end of a block when a write multiple blocks command
is in flight.
The easy fix is to simply get rid of all the IRQ driven logic and make
the driver push as much data into the FIFO as it can. That way we never
drain and we never run into the problem.
Reported-by: Jan Leonhardt <jan@cyberdesigner.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
Add derivative of the rcar_i2c driver which is capable of
probing itself from DM and uses DT.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Remove the rcar_i2c driver, since it's no longer used by any
board and will be superseded by a DM and DT capable variant.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
devm_zalloc() is already defined in dm/device.h header, so
devm_zalloc can be removed from linux_compact.h beader file.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Switch to DM_USB was done and there is no need to keep !DM_USB code in
tree.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
By enabling BLK by default this is the next driver which needs to get
support for DM_USB. Adding generic DWC3 glue logic which only
parse nodes and read device mode. Based on it probe proper
host/peripheral DWC3 drivers for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support to get maximum speed from dt so that usb drivers
makes use of it for DT parsing.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
(rebase and fix errors)
Reviewed-by: Simon Glass <sjg@chromium.org>
The patch is preparing dwc3 core for enabling DM_USB with peripheral
driver with using driver model support.
The driver will be bound by the DWC3 wrapper driver based on the
dr_mode device tree entry.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
(Remove dwc3-omap changes)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds phy tranceiver driver for STM32 USB PHY
Controller (usbphyc) that provides dual port High-Speed
phy for OTG (single port) and EHCI/OHCI host controller
(two ports).
One port of the phy is shared between the two USB controllers
through a UTMI+ switch.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
During file download, it only uses 32bit variable for file size and
it limits maximum file size less than 4GB. Update to support more
than 4GB file with using two 32bit variables for file size as thor
protocol 5.0.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
The thor sender can send filename without null character and it is
used without consideration of overflow. Actually, character array
for filename is assigned with DEFINE_CACHE_ALIGN_BUFFER() and it
is bigger than size of memcpy, so there was no real overflow.
Fix filename overflow for code level integrity.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
This change enables support for MC34708 PMIC in sandbox. Now we can
emulate the I2C transfers larger than 1 byte.
Notable changes for this driver:
- From now on the register number is not equal to index in the buffer,
which emulates the PMIC registers
- The PMIC register's pool is now dynamically allocated up till
64 regs * 3 bytes each = 192 B
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds support for MC34708 PMIC, to be used with driver model
(DM).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit provides support for transmissions larger than 1 byte for
PMIC devices used with DM (e.g. MC34708 from NXP).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
The struct uc_pmic_priv's trans_len field stores the number of types to
be transmitted per PMIC transfer.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
When Kconfig support was added for MVGBE it included automatically
selected PHYLIB support. But MVGBE does not need PHYLIB it will build
fine without it. Commit ed52ea507f ("net: add Kconfig for MVGBE")
should have been a no-op in terms of build size but because of the
selecting PHYLIB the openrd configs increased in size.
Remove the automatic selection of PHYLIB, boards that need it will have
already enabled it in their config header file.
Fixes: commit ed52ea507f ("net: add Kconfig for MVGBE")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Not all the udevice have a available DT node, eg. rksdmmc@ff500000.blk
which add by mmc_bind(), these device do not have/need set pinctrl
state.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h
To address that situation we discussed on the list moving to
genetic_set_bit() instead.
Doing a quick grep for similar situations in drivers/usb shows that the
composite device is using __set_bit().
This patch switches over to generic_set_bit to maintain consistency between
the two gadget drivers.
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
Compiling the f_mass_storage driver for an x86 target results in a
compilation error as set_bit and clear_bit are provided by bitops.h
Looking at the provenance of the current u-boot code and the git change
history in the kernel, it looks like we have a local copy of set_bit and
clear_bit as a hold-over from porting the Linux driver into u-boot.
These days __set_bit and __clear_bit are optionally provided by an arch and
can be used as inputs to generic_bit_set and generic_bit_clear.
This patch switches over to generic_set_bit and generic_clear_bit to
accommodate.
Tested on i.MX WaRP7 and Intel Edison
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Lukasz Majewski <lukma@denx.de>
Cc: Marek Vasut <marex@denx.de>
mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code.
When imported into u-boot we need to add the appropriate SPDX tag and
re-format it slightly.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
This commit adds basic support for PWM found on Allwinner A64.
It can be used for pwm_backlight driver (e.g. for Pinebook)
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Currently dw_hdmi configures HSYNC polarity using VSYNC setting from
EDID and vice versa. Fix it, since it breaks displays where HSYNC
and VSYNC polarity differs
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
The check is necessary to avoid NULL pointer dereference.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Nothing defines CONFIG_DOVE so remove the code that uses it.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Since b0ba1e7e9d
(rockchip: clk: rk3288: add clk_enable function and support USB HOST0/HSIC)
Ethernet no longer probes on RK3288.
Add no-ops for GMAC clocks observed to be requested which match the
clk_enable cases in RK3368 and RK3399.
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Cc: Wadim Egorov <w.egorov@phytec.de>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".
Signed-off-by: Marek Behun <marek.behun@nic.cz>
Signed-off-by: Stefan Roese <sr@denx.de>
Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
