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Merge branch 'master' of git://git.denx.de/u-boot-video

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This commit is contained in:
Tom Rini 2018-05-15 08:29:24 -04:00
commit c75990889d
8 changed files with 212 additions and 4 deletions
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9
arch/arm/dts/sun50i-a64.dtsi
View file

@ -319,6 +319,15 @@
};
};
pwm: pwm@01c21400 {
compatible = "allwinner,sun50i-a64-pwm",
"allwinner,sun5i-a13-pwm";
reg = <0x01c21400 0x8>;
clocks = <&osc24M>;
#pwm-cells = <3>;
status = "disabled";
};
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;

1
arch/arm/include/asm/arch-sunxi/gpio.h
View file

@ -172,6 +172,7 @@ enum sunxi_gpio_number {
#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
#define SUNXI_GPD_PWM 2
#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3

12
arch/arm/include/asm/arch-sunxi/pwm.h
View file

@ -10,8 +10,15 @@
#define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4)
#define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf)
#define SUNXI_PWM_CTRL_PRESCALE0_MASK 0xf
#define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4)
#define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5)
#define SUNXI_PWM_CTRL_CH0_ACT_STA BIT(5)
#define SUNXI_PWM_CTRL_CLK_GATE BIT(6)
#define SUNXI_PWM_CH0_PERIOD_MAX (0xffff)
#define SUNXI_PWM_CH0_PERIOD_PRD(x) ((x & 0xffff) << 16)
#define SUNXI_PWM_CH0_PERIOD_DUTY(x) ((x) & 0xffff)
#define SUNXI_PWM_PERIOD_80PCT 0x04af03c0
@ -30,4 +37,9 @@
#define SUNXI_PWM_MUX SUN8I_GPH_PWM
#endif
struct sunxi_pwm {
u32 ctrl;
u32 ch0_period;
};
#endif

7
drivers/pwm/Kconfig
View file

@ -43,3 +43,10 @@ config PWM_TEGRA
four channels with a programmable period and duty cycle. Only a
32KHz clock is supported by the driver but the duty cycle is
configurable.
config PWM_SUNXI
bool "Enable support for the Allwinner Sunxi PWM"
depends on DM_PWM
help
This PWM is found on H3, A64 and other Allwinner SoCs. It supports a
programmable period and duty cycle. A 16-bit counter is used.

1
drivers/pwm/Makefile
View file

@ -15,3 +15,4 @@ obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
obj-$(CONFIG_PWM_ROCKCHIP) += rk_pwm.o
obj-$(CONFIG_PWM_SANDBOX) += sandbox_pwm.o
obj-$(CONFIG_PWM_TEGRA) += tegra_pwm.o
obj-$(CONFIG_PWM_SUNXI) += sunxi_pwm.o

178
drivers/pwm/sunxi_pwm.c Normal file
View file

@ -0,0 +1,178 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
*/
#include <common.h>
#include <div64.h>
#include <dm.h>
#include <pwm.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/pwm.h>
#include <asm/arch/gpio.h>
#include <power/regulator.h>
DECLARE_GLOBAL_DATA_PTR;
#define OSC_24MHZ 24000000
struct sunxi_pwm_priv {
struct sunxi_pwm *regs;
bool invert;
u32 prescaler;
};
static const u32 prescaler_table[] = {
120, /* 0000 */
180, /* 0001 */
240, /* 0010 */
360, /* 0011 */
480, /* 0100 */
0, /* 0101 */
0, /* 0110 */
0, /* 0111 */
12000, /* 1000 */
24000, /* 1001 */
36000, /* 1010 */
48000, /* 1011 */
72000, /* 1100 */
0, /* 1101 */
0, /* 1110 */
1, /* 1111 */
};
static int sunxi_pwm_config_pinmux(void)
{
#ifdef CONFIG_MACH_SUN50I
sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
#endif
return 0;
}
static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
struct sunxi_pwm_priv *priv = dev_get_priv(dev);
debug("%s: polarity=%u\n", __func__, polarity);
priv->invert = polarity;
return 0;
}
static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
uint period_ns, uint duty_ns)
{
struct sunxi_pwm_priv *priv = dev_get_priv(dev);
struct sunxi_pwm *regs = priv->regs;
int prescaler;
u32 v, period = 0, duty;
u64 scaled_freq = 0;
const u32 nsecs_per_sec = 1000000000U;
debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
for (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK;
prescaler++) {
if (!prescaler_table[prescaler])
continue;
scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
if (period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)
break;
}
if (period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
debug("%s: failed to find prescaler value\n", __func__);
return -EINVAL;
}
duty = lldiv(scaled_freq * duty_ns, nsecs_per_sec);
if (priv->prescaler != prescaler) {
/* Mask clock to update prescaler */
v = readl(&regs->ctrl);
v &= ~SUNXI_PWM_CTRL_CLK_GATE;
writel(v, &regs->ctrl);
v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
v |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
writel(v, &regs->ctrl);
v |= SUNXI_PWM_CTRL_CLK_GATE;
writel(v, &regs->ctrl);
priv->prescaler = prescaler;
}
writel(SUNXI_PWM_CH0_PERIOD_PRD(period) |
SUNXI_PWM_CH0_PERIOD_DUTY(duty), &regs->ch0_period);
debug("%s: prescaler: %d, period: %d, duty: %d\n",
__func__, priv->prescaler,
period, duty);
return 0;
}
static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
{
struct sunxi_pwm_priv *priv = dev_get_priv(dev);
struct sunxi_pwm *regs = priv->regs;
u32 v;
debug("%s: Enable '%s'\n", __func__, dev->name);
v = readl(&regs->ctrl);
if (!enable) {
v &= ~SUNXI_PWM_CTRL_ENABLE0;
writel(v, &regs->ctrl);
return 0;
}
sunxi_pwm_config_pinmux();
if (priv->invert)
v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
else
v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
v |= SUNXI_PWM_CTRL_ENABLE0;
writel(v, &regs->ctrl);
return 0;
}
static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
{
struct sunxi_pwm_priv *priv = dev_get_priv(dev);
priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);
return 0;
}
static int sunxi_pwm_probe(struct udevice *dev)
{
return 0;
}
static const struct pwm_ops sunxi_pwm_ops = {
.set_invert = sunxi_pwm_set_invert,
.set_config = sunxi_pwm_set_config,
.set_enable = sunxi_pwm_set_enable,
};
static const struct udevice_id sunxi_pwm_ids[] = {
{ .compatible = "allwinner,sun5i-a13-pwm" },
{ .compatible = "allwinner,sun50i-a64-pwm" },
{ }
};
U_BOOT_DRIVER(sunxi_pwm) = {
.name = "sunxi_pwm",
.id = UCLASS_PWM,
.of_match = sunxi_pwm_ids,
.ops = &sunxi_pwm_ops,
.ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
.probe = sunxi_pwm_probe,
.priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),
};

4
drivers/video/dw_hdmi.c
View file

@ -401,11 +401,11 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi,
/* set up hdmi_fc_invidconf */
inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);

4
drivers/video/sunxi/sunxi_dw_hdmi.c
View file

@ -303,10 +303,10 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
setbits_le32(&phy->pol, 0x200);
if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW)
if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW)
setbits_le32(&phy->pol, 0x100);
setbits_le32(&phy->ctrl, 0xf << 12);