Commit graph

2097 commits

Author SHA1 Message Date
Tom Rini
d94604d558 Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEorkTmaQ1QAtDiYw67UVZlNoLnbQFAlwOzFoACgkQ7UVZlNoL
 nbQUdQ//SRRBfjUe8RYTbojvTGQav0GTxnMkz4GFSrqu0nvGMW2YSlheOMqq72sg
 rK5mQqDvdkItCn+G8AZ5NV2ijkQ7NQWCfqL3EtApzTpv6qjfgv7xvopz8q4NZvzB
 Wp+4cFf9YQjNwhJ7kLvWHB7SBiz9AfMYRAj9cscH9xsGL3HxPj62WDfwyK/QXana
 KIxRKQ26/1AdOZy272yv70vlFj4IwForxV3ACimsWRuYcb8yre3pE0tD7XpMCSNv
 9GOfL7r4LS7U0+QnJoVeYLMhttRvOGJNUYtO2+ImO5NC3u9v8ehYEQ3FjGmM69CB
 vuPDQBDQc+Ap+Iu3k18PYSstp+mc9fbe9SQdlx6ARAecQqWTN4EOhf8s3m2bQq3S
 B58I0Zvowcdm8V2JKdXw94UqZX862U8PWH0BmcuX+4k+kRDwwU4XQY2nLp+Htz1w
 2q6vEdKGj7YUOaomx9fmKRL+9BFGoD+M9mTiHOwzqwxy6Pa9VkruSvMErM7p2l/z
 xI/Q+xPJhyk5TXgZRsz4Nat59WpifWruibKEd4PArQ446heHWmzLWjw/MWiFyd/H
 agCdpDZVJ8R7h1Krs+Ez8XjR1Qcg0gs+CdNBuvqxzOpMQGGonXA1nwi8YfHykhII
 urfoC8pew1yxiLGw7J2JSX808HV/09WCSEsrOOhE3T78rXTDlS4=
 =aT7d
 -----END PGP SIGNATURE-----

Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriq

Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC

[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-10 17:19:59 -05:00
Philipp Tomsich
a740ee913e lib: merge CRC16-CCITT into u-boot/crc.h
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-12-08 20:18:32 -05:00
Priyanka Jain
4909b89ec7 armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs

Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:19 -08:00
Rajesh Bhagat
382c53f946 net: fm: add TFABOOT support
Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.

Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix checkpatch issues]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06 14:37:42 -08:00
Tom Rini
2a055ea532 Minor sandbox enhancements / fixes
tpm improvements to clear up v1/v2 support
 buildman toolchain fixes
 New serial options to set/get config
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAlwIe0gRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreY02wgAjK9U1ADmoNi4xWgtq83EerxOGTq68BRD
 CfnUDgI+FQHNv/LxdZ8lZ2lgGG1xXZ8mdeHWghllHoLEnwMQ3LxfDRnpkyC6VBE9
 LvZF4F7BhTnGsKImlloQ5oMhKI4sDKjqRkRL3D633x5dq9Z571obAyGwLMo67vv6
 U8iv1mRMr6au46pLvH25DF6h5LuM7TBSJVDlzmFmmD++r/YDroTJfo07qdo8sNqS
 0hDPjgp3uqf1mX2cbNHk56a3DmO9fL6Gcvdv0LHGQvRyfQ36TY+cEcDU2y2p+tl+
 t1LFamfZvalix9AyJegr3qGMOb9B20ar89EItXzH9J+ahnlZmEat+w==
 =VAMW
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-5dec18' of git://git.denx.de/u-boot-dm

Minor sandbox enhancements  / fixes
tpm improvements to clear up v1/v2 support
buildman toolchain fixes
New serial options to set/get config
2018-12-05 20:32:25 -05:00
Tom Rini
9450ab2ba8 Merge branch 'master' of git://git.denx.de/u-boot-spi
- Various MTD fixes from Boris
- Zap various unused / legacy paths.
- pxa3xx NAND update from Miquel

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-12-05 15:06:24 -05:00
Simon Glass
e628bba785 sandbox: net: Correct name copy in eth_raw_bus_post_bind()
We cannot be sure that the interface name takes up the full length of the
space available to it. Use strcpy() instead of memcpy() in this case. This
corrects a valgrind warning.

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-12-05 06:01:34 -07:00
Tom Rini
0a3d59e010 Xilinx changes for v2019.01
microblaze:
 - Use default functions for memory decoding
 - Showing model from DT
 
 zynq:
 - Fix spi flash DTs
 - Fix zynq_help_text with CONFIG_SYS_LONGHELP
 - Tune cse/mini configurations
 - Enabling cse/mini testing with current targets
 
 zynqmp:
 - Enable gzip SPL support
 - Fix chip detection logic
 - Tune mini configurations
 - DT fixes(spi-flash, models, clocks, etc)
 - Add support for OF_SEPARATE configurations
 - Enabling mini testing with current targets
 - Add mini mtest configuration
 - Some minor config setting
 
 nand:
 - arasan: Add subpage configuration
 
 net:
 - gem: Add 64bit DMA support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlwFUAkACgkQykllyylKDCHtIACeO2G+jfSPxIjsyuPWbRup4e+A
 H5UAn3knKDNJ3VVidqO1C5o8Ye5JePZF
 =lW3g
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2019.01' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2019.01

microblaze:
- Use default functions for memory decoding
- Showing model from DT

zynq:
- Fix spi flash DTs
- Fix zynq_help_text with CONFIG_SYS_LONGHELP
- Tune cse/mini configurations
- Enabling cse/mini testing with current targets

zynqmp:
- Enable gzip SPL support
- Fix chip detection logic
- Tune mini configurations
- DT fixes(spi-flash, models, clocks, etc)
- Add support for OF_SEPARATE configurations
- Enabling mini testing with current targets
- Add mini mtest configuration
- Some minor config setting

nand:
- arasan: Add subpage configuration

net:
- gem: Add 64bit DMA support
2018-12-03 19:30:54 -05:00
Siva Durga Prasad Paladugu
5f68f44c14 net: zynq_gem: Add check for 64-bit dma support by hardware
This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2018-12-03 16:22:06 +01:00
Vipul Kumar
9a7799f4f4 net: zynq_gem: Added 64-bit addressing support
This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.

Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
2018-12-03 16:22:01 +01:00
Tom Rini
93e72ac472 Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
 - net: designware: add meson meson compatibles
 - Amlogic Meson cleanup for AXG SoC support
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJb/AwoAAoJEHfc29rIyEnR2dMQANCsuWQzKASCLgUzeL/KWhQ8
 gj1YEVGbS0meQ35hNo0hL6qfN4VkjazawyWnb40HVVADBjil42QuxN9rncovg69Q
 ZvPEo4XYNCkDzOU3UmoR2rjxxGICVFY6GCOuNbqzvB2x4gWJmoUeByqewKW2g2Zp
 jyjbzYvJ+r8wLtUFbdqaGvsHHC8hiIkjyeaqdXUc6NHJrGYasRuOsCO92bEioYC1
 XPh76c2ABAnbzJy7GArdlBbDOQrQxoEskVeP47ZjiPywXxGCkgHaRSXaUKzpz30G
 8MrA5AciL6pmurmsM0APlgvJwL7qaX1P6NxiJ+12prWWfAk1ZC2/MEKVZY+gO/CF
 vUAyzhus1oJ5JjccCngy/1ftkIReueSbUrzGYFvqhihs9g4QyRpi7F5MDKX0MvP2
 uk+XXStXs+rOZ2YdMFlV8l6G12TijcViZVmVHdh8qdl4t8WFlv7gENVUM+0mhyu2
 x5OsoYz5w2h9hCh/CB3oIZfyJBe5VZVHZ2fWIRZJ72J7toUGMewlKYQq2LOv7A9q
 w6vRGnza3fSPUZgYenznohaeo9vXG/WX7cNSPQiNBoiGeC+Y2ko5NHe2MIEnUD4c
 amp21KA6rWnWeHHvDbwo5DJ+NhCd6uMgkiZDLCuiTtns1/a03l0V6kgOvQLIBjhK
 KxBWBn6+rDPq1wJxhxab
 =Oo1g
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support
2018-11-29 15:16:58 -05:00
Jagan Teki
e2cae51472 spi: Remove unused spi_init
Remove spi_init definition which never used on
respective code since from many years.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-11-27 21:06:53 +05:30
Neil Armstrong
71a38a8e8e net: designware: add meson meson axg compatible
Add the compatible string for the upcoming Amlogic AXG SoC family.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:10 +01:00
Neil Armstrong
ec353ad1b6 net: designware: add meson meson gxbb compatible
Add the compatible string for the Amlogic GXBB SoC family.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-11-26 14:40:10 +01:00
Icenowy Zheng
9b16ede4a4 sun8i_emac: add support for setting EMAC TX/RX delay
Some boards have the EMAC TX/RX lanes wired with a different length with
the clock lane, which can be workarounded by setting a TX/RX delay in
the EMAC.

This kind of delays are already defined in the newest device tree
binding of dwmac-sun8i, which has already entered linux-next.

Add support for setting these delays.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-23 11:01:09 +05:30
Grygorii Strashko
79d8127168 driver: net: ti: keystone_net: switch to use common mdio lib
Update TI Keystone 2 driver to re-use common mdio lib.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:01 -06:00
Grygorii Strashko
4f41cd9a95 driver: net: ti: cpsw: switch to use common mdio lib
Update TI CPSW driver to re-use common mdio lib

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:01 -06:00
Grygorii Strashko
6c4bbccc6e driver: net: ti: introduce common mdio support library
All existing TI SoCs network HW have similar MDIO implementation, so
introduce common mdio support library which can be reused by TI networking
drivers.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:42:00 -06:00
Grygorii Strashko
cbec53b434 driver: net: ti: cpsw: update to use SPDX identifier
Update to use SPDX license identifier.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:00 -06:00
Grygorii Strashko
af0cf2178b drivers: net: keystone_net: drop non dm code
Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:42:00 -06:00
Grygorii Strashko
6a256a8ed4 configs: net: convert DRIVER_TI_KEYSTONE_NET kconfig
Convert DRIVER_TI_KEYSTONE_NET to Kconfig.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:41:59 -06:00
Grygorii Strashko
ffad5fa0cd driver: net: consolidate ti's code in separate folder
Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.

Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2018-11-05 10:41:59 -06:00
Quentin Schulz
05bbd676a7 net: phy: mscc: add support for VSC8574 PHY
The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:59 -06:00
Quentin Schulz
b5bca65e19 net: phy: mscc: factorize part of config function for VSC8584
Part of the config is common between the VSC8584 and the VSC8574, so to
prepare for the upcoming support of VSC8574, use the phy_device.priv
pointer that will keep the function that holds code that is PHY-specific
and that should be called during config function.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Quentin Schulz
04087fc494 net: phy: mscc: add support for VSC8584 PHY
The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with the
MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set
the blinking pattern of each of its 4 LEDs, supports hardware offloading
of MACsec and supports SyncE as well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8584 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

The revA of the VSC8584 PHY (which is not and will not be publicly
released) should NOT patch the firmware of the microcontroller or it'll
make things worse, the easiest way is just to not support it.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Cédric Le Goater
e6ddacc2d0 net: ftgmac100: Add support for the Aspeed SoC
The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:58 -06:00
Cédric Le Goater
1c0c61e927 net: ftgmac100: add clock support
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
d0e0b84c66 net: ftgmac100: handle timeouts when transmitting
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
e766849713 net: ftgmac100: convert the RX/TX descriptor arrays
Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
538e75d3fc net: ftgmac100: add MDIO bus and phylib support
Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:57 -06:00
Cédric Le Goater
591ffd98b0 net: ftgmac100: use setbits_le32() in the reset method
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Cédric Le Goater
f95de0bd10 net: ftgmac100: convert to driver model
The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Cédric Le Goater
3bd796351f net: ftgmac100: use the aligned() macro
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Cédric Le Goater
f72b4a3dde net: ftgmac100: use the BIT() macro
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Stefan Roese
c895ef4650 net: Add MT7628 ethernet driver
This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs
(e.g. MT7628 and MT7688), including a minimum setup of the integrated
switch. This driver is loosly based on the driver version included in
this MediaTek github repository:

https://github.com/MediaTek-Labs/linkit-smart-uboot.git

Tested on the MT7688 LinkIt smart-gateway and on the
Gardena-smart-gateway.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Frank Wunderlich <frankwu@gmx.de>
Cc: Weijie Gao <hackpascal@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-11-05 10:41:56 -06:00
Bin Meng
db148f2a69 powerpc: t1040: Correct RCW EC2 settings
Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.

- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
  be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
  macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 13:19:43 -07:00
Patrick Delaunay
22929e1266 drivers: cosmetic: Convert SPDX license tags to Linux Kernel style
Complete in the drivers directory the work started with
commit 83d290c56f ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-28 09:26:39 -04:00
Anatolij Gustschin
58ec4d3342 net: fec_mxc: add support for i.MX8X
Add compatible property and enable the FEC ipg clock when probing
on i.MX8X. Add specific function for reading FEC clock rate via
clock driver when configuring MII speed register. Allow FEC_MXC
selection for i.MX8.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:38 -05:00
Baruch Siach
18593fa80b net: mvpp2: increase PHY reset pulse
The default Linux PHY reset delay is 10ms. This is also the requirement
for Marvell 88E151x PHYs, which are likely to be used with this Ethernet
MAC.

Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24 14:45:38 -05:00
Baruch Siach
fa14027d5c net: mvpp2: fix polarity of PHY reset signal
The dm_gpio_set_value() call sets the logical level of the GPIO signal.
That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The
driver needs to assert the reset, and then deassert it. Not the other
way around.

Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-10-24 14:45:38 -05:00
Martin Fuzzey
0126c641e8 net: dm: fec: Obtain the transceiver type from the DT
The DT property "phy-mode" already provides the transceiver type.
Use it so that we do not have to also set CONFIG_FEC_XCV_TYPE

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Martin Fuzzey
ad8c43cbca net: dm: fec: Support the phy-supply binding
Configure the phy regulator if defined by the "phy-supply" DT phandle.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Martin Fuzzey
331fcabe4f net: dm: fec: Fix phy-reset-duration clamping and defaults
The DT binding says:
- phy-reset-duration : Reset duration in milliseconds.  Should present
  only if property "phy-reset-gpios" is available.  Missing the property
  will have the duration be 1 millisecond.  Numbers greater than 1000 are
  invalid and 1 millisecond will be used instead.

However the current code:
 - clamps values greater than 1000ms to 1000ms rather than 1.
 - does not initialize the delay if the property does not exist
   (else clause mismatch)
 - returns an error if phy-reset-gpios is not defined

Fix all this and simplify by using dev_read_u32_default()

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Martin Fuzzey
9b8b918884 net: dm: fec: Fix time unit error in phy-reset-duration
The DT binding says that phy-reset-duration is in ms, but the driver
currently uses udelay().

Switch to mdelay() to fix this.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Jeremy Gebben
30a2c8cca8 net: phy: aquantia: autodetect if firmware needs to be loaded
If the phy reports a valid firmware version and doesn't indicate
a fault, skip loading the firmware.  This allows the same image
to be used on boards that have firmware storage and those that do not.

Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Jeremy Gebben
4506423ad2 net: phy: aquantia: add firmware loading support
Aquantia phys have firmware that can be loaded automatically
from storage directly attached to the phy or via MDIO commands.
Add support for loading firmware from either a file or a
raw location on an MMC device.

Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:37 -05:00
Jeremy Gebben
1c6501088e configs: migrate CONFIG_PHY_AQUANTIA to Kconfig
The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G.

Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-24 14:45:36 -05:00
Michal Simek
3dc80934f4 net: gem: Do not setup any clock for Xilinx SoC Versal
Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Michal Simek
ec48b6c991 arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:21 +02:00
Tom Rini
15f22ac2ee ldpaa_eth.c: Fix warning when PHYLIB is not enabled
We need to #ifdef some variables to avoid warning about them being
unused.

Fixes: 1a048cd656 ("driver: net: fsl-mc: Add support of multiple phys for dpmac")
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-12 07:41:24 -04:00
Pankaj Bansal
1a048cd656 driver: net: fsl-mc: Add support of multiple phys for dpmac
Till now we have had cases where we had one phy device per dpmac.
Now, with the upcoming products (LX2160AQDS), we have cases, where there
are sometimes two phy devices for one dpmac. One phy for TX lanes and
one phy for RX lanes. to handle such cases, add the support for multiple
phys in ethernet driver. The ethernet link is up if all the phy devices
connected to one dpmac report link up. also the link capabilities are
limited by the weakest phy device.

i.e. say if there are two phys for one dpmac. one operates at 10G without
autoneg and other operate at 1G with autoneg. Then the ethernet interface
will operate at 1G without autoneg.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:45:28 -05:00
Pankaj Bansal
1ed19a1421 driver: net: fsl-mc: initialize dpmac irrespective of phy
The dpmac initalization should not depend on phy.
As the phy is not necessary to be present for dpmac to function.
Therefore, remove dpmac initialization dependency from phy.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:45:23 -05:00
Pankaj Bansal
a3cb5340f1 driver: net: fsl-mc: Modify the dpmac link detection method
when there is no phy present for a dpmac, a dummy phy device is created.
when we move to multiple phy method, we need to create as many dummy phy
devices.

Change this method so that we don't need to create dummy phy devices.
We always report linkup if no phy is present.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:45:01 -05:00
Pankaj Bansal
f259c43d89 driver: net: fsl-mc: fix error handing in init_phy
if an error occurs during init_phy, we should free the phydev structure
which has been allocated by phy_connect.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:43:18 -05:00
Pankaj Bansal
d75e81d9e0 driver: net: fsl-mc: remove unused strcture elements
The phydev structure is present in both ldpaa_eth_priv and
wriop_dpmac_info. the phydev in wriop_dpmac_info is not being used

As the phydev is created based on phy_addr and bus members of
wriop_dpmac_info, it is appropriate to keep phydev in wriop_dpmac_info.

Also phy_regs is not being used, therefore remove it

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:36:34 -05:00
Pankaj Bansal
afd6c6b470 driver: net: fsl-mc: modify the label name
The goto label name is misspelled it should be DPMAC not DPAMC

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:30:28 -05:00
Joe Hershberger
72ff004258 test: eth: Add a test for the target being pinged
The target will respond to pings while doing other network handling.
Make sure that the response happens and is correct.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
45988dae4c test: eth: Add a test for ARP requests
This tests that ARP requests made to this target's IP address are
responded-to by the target when it is doing other networking operations.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
9cbe5972c3 net: sandbox: Add a priv ptr for tests to use
Tests need to be able to pass their "unit test state" to the handlers
where asserts are evaluated. Add a function that allows the tests to set
this private data on the sandbox eth device.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:59 -05:00
Joe Hershberger
c67a420781 net: sandbox: Allow fake eth to handle more than 1 packet response
Use up to the max allocated receive buffers so as to be able to test
more complex situations.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:58 -05:00
Joe Hershberger
76a503439e net: sandbox: Share the priv structure with tests
If tests want to implement tx handlers, they will likely need access to
the details in the priv structure.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
c7eb733d60 net: sandbox: Make the fake eth driver response configurable
Make the send handler registerable so tests can check for different
things.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
e95bb16110 net: sandbox: Refactor sandbox send function
Make the behavior of the send function reusable.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:56 -05:00
Joe Hershberger
e4ab9a6508 net: sandbox: Move disabled flag into priv struct
Store the per-device data with the device.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:56 -05:00
Janine Hagemann
0f347a0096 net: phy: ti: Add binding for the CLK_OUT pin muxing
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:54 -05:00
Janine Hagemann
be71a74c59 net: phy: ti: Recover from "port mirroring" N/A MODE4
The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.

To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).

To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.

Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"

https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954

Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring"
N/A MODE4") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2018-10-10 12:28:54 -05:00
Janine Hagemann
fba725f410 net: phy: ti: Add lane swapping support in the DP83867 TI's PHY driver
This patch adds support for enabling or disabling the lane swapping
(called "port mirroring" in PHY's CFG4 register) feature of the DP83867
TI's PHY device.

One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).

Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping
support in the DP83867 TI's PHY driver") of mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:53 -05:00
Bin Meng
dda5251037 net.h: Include linux/if_ether.h to avoid duplication
There are plenty of existing drivers that have macros like ETH_ALEN
defined in their own source files. Now that we imported the kernel's
if_ether.h to U-Boot we can reduce some duplication.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-10 12:28:52 -05:00
Bin Meng
339613eba5 net: pch_gbe: Make probe/remove static
These two routines are internal to pch_gbe driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-09 14:18:21 -05:00
Bin Meng
b06d76f9ae linux/compat.h: Add netdev_### log macros
Currently there are two ethernet drivers (mvneta.c and mvpp2.c) that
has netdev_### (eg: netdev_dbg) log macros defined in its own driver
file. This adds these log macros in a common place linux/compat.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-09 14:18:17 -05:00
Janine Hagemann
3d1bd5b590 net: gmac_rockchip: Add handling for RGMII_ID/RXID/TXID
Using PHY internal delays in combination with the phy-mode
rgmii-id/rxid/txid was not possible. Only rgmii was supported.

Now we can disable rockchip's gmac delay lines and also use
rgmii-id/rxid/txid.

Based on commit eaf70ad14cbb ("net: stmmac: dwmac-rk: Add
handling for RGMII_ID/RXID/TXID") for mainline linux kernel.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Janine Hagemann
04acabd22c net: gmac_rockchip: Fix a register write in rk3328_gmac_set_to_rgmii
We have to use RK3328_RXCLK_DLY_ENA_GMAC_ENABLE instead of
RK3328_RXCLK_DLY_ENA_GMAC_MASK in rk3328_gmac_set_to_rgmii()
to enable the RX delay.
The MASK was used in a wrong way.

Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Reviewed-by: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-10-04 21:15:46 +02:00
Tom Rini
27f622d568 Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
 Switch to driver model for SATA on LS1021A and LS1043A.
 Add support for LS1012AFRWY rev C board.
 Enable SMMU for LS1043A.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJbrkHRAAoJEO1FWZTaC520r3UQAIBntTglI1QK7YizVxZ1x9DL
 42oSEIwkuN0wbndR7Jzx4EPPFJ8yX4v3stoxC3qS5DQ9kHMzuqRQcIDYbcn5Qy7Z
 vd0mBUmpkRjr988pSaSHVQ8kPasncb545fCUumrXrCmhuG5Ea2Itw1zLdsTf7X5n
 39KxFUOAR63BDCT0ZlR4VyMo01GxxHWCzRQH/rOWVzOcJsWF7R52hWIBBzVDxKPv
 HF9SYaAB0PTFgSjJx5wYQ4xPdHVUp+svtYSJE8JYzEr/BvOVtL2iEi4t2rk19CrX
 IaVMFydlv2iDgWdoSZFCCN/6lGDWSv1LWPDglWhLQhOYvrJOjZfgzzeAGU7wqoz4
 JVjSLf6dHeOma55dbP/epDmyDFqWIfNOQ3uP4RM57xJ0PXQuT7ACVJctr6kHVTGL
 1ZZxPdKSSf9lvtzoogPTTYRD5Ry7ud3sYZ0v3OHN1sbVcaHaVoHPeXeSz1sLg3Q+
 zhUo1lXx4FcTz9R1fafdcqqAk/YGMZ7sBE+uYJPgExnApxrZID9IiOdGIBxo8jiK
 ozLmaCIDqRyu/qhQW9WMri1tvYdKwq/739gBvvcIcrLR5RzfNUdwWjhtBokPQQnS
 WZNqd3/0N8ZFGz7V0GOxCDnAo4nwQeZVFGMtTpoCtjPvr6DWBHsEUlQHTT3dQKz/
 TXygMYUYGA+/vux0Dt4I
 =XRFI
 -----END PGP SIGNATURE-----

Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
2018-09-29 11:47:32 -04:00
Zhao Qiang
db947fa038 net: fman: Support both new and legacy FMan Compatibles
Recently the FMan Port and MAC compatibles were changed. This patch
aligns the FMan Port and MAC compatibles to the new FMan device tree
binding document. The FMan device tree binding document can be found
in the Linux kernel version 3.18.0, commit
297d35fd2a7d3fbd4e5c0f0c1c18213117ba11ba
./Documentation/devicetree/bindings/powerpc/fsl/fman.txt

This patch doesn't affect legacy compatibles support.

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:01:27 -07:00
Pramod Kumar
7abf92327f ls1012a: remove debug info from u-boot log
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:58:42 -07:00
Prabhakar Kushwaha
87519a9ece driver: net: fsl-mc: Memset MC reserve ram memory before usage
Memory reserved for Management Complex needs to be cleaned before any
usage.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
[York S: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:55:21 -07:00
Nipun Gupta
a78df40cba u-boot: fixup the iommu-map property of fsl-mc node
The iommu-map property in the fsl-mc node is updated by
valid stream-ids by u-boot. This patch is to fixup this
property for LS208x and LS1088.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:55:05 -07:00
Yinbo Zhu
c3ced8a6ed ppa/fm/qe: use block layer in ppa/fm/qe driver
At present the MMC subsystem maintains its own list of MMC devices.
This cannot work with driver model when CONFIG_BLK is enabled, use
blk_dread to replace previous mmc read interface, use
mmc_get_blk_desc to get the mmc device property.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:48:51 -07:00
Tom Rini
bbef20d479 Xilinx changes for v2018.11
- Handle BOARD_LATE_INIT via Kconfig
 
 SPL:
 - Enable GZIP for all partitions types(not only for kernel)
 
 ZynqMP:
 - Rearrange pmufw version handling
 - Support newer PMUFW with improved fpga load sequence
 
 Zynq:
 - Cleanup config file
 - Simplify zybo config by enabling option via Kconfig
 
 net:
 - Fix gems max-speed property reading
 - Enable support for fixed-link phys
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAluss3IACgkQykllyylKDCFQWwCfc7bvoUN1vevGYTfcG2cEYSF5
 IxQAoI/10FGWJS6rgTG0IVFvoSI1ALhA
 =Q/Tg
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for kernel)

ZynqMP:
- Rearrange pmufw version handling
- Support newer PMUFW with improved fpga load sequence

Zynq:
- Cleanup config file
- Simplify zybo config by enabling option via Kconfig

net:
- Fix gems max-speed property reading
- Enable support for fixed-link phys
2018-09-27 08:29:10 -04:00
Michal Simek
3888c8d197 net: zynq_gem: Add support for fixed-link phy
Based on dt-specs fixed-link doesn't require phy-handle to be used.
Fix driver to only read phy related setting when phy-handle is found.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-09-27 07:59:26 +02:00
Siva Durga Prasad Paladugu
f213dbbdec net: zynq_gem: Fix reading of max-speed property
max-speed property is part of phynode and it has to be
read using ofnode_read_u32_default(). This fixes the issue
of incorrect max-speed read from DT.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Sekhar Nori
e2597be5bc drivers: net: cpsw: add support to update phy address
On some boards using TI CPSW, it may be possible that
PHY address was not latched correctly, and the actual
address that the phy responds on is different from that
set in device-tree. For example, see this problem report
on beaglebone black:

https://groups.google.com/d/msg/beagleboard/9mctrG26Mc8/1FuI_i5KW10J

Add support to check for this condition and use the
detected phy address when its safe to do so.

Also, add a public API that exposes the phy address of
a given slave. This can be used to update device-tree that
is passed to Linux kernel.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2018-09-25 21:49:18 -04:00
Adam Ford
d7869b2183 Convert CONFIG_MII et al to Kconfig
This converts the following to Kconfig:
   CONFIG_MII
   CONFIG_DRIVER_TI_EMAC

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-08-17 13:03:54 -04:00
Tom Rini
719afeb0b3 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-08-17 07:24:34 -04:00
Marek Vasut
215a06565a net: designware: socfpga: Add Arria10 extras
Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-08-13 22:35:42 +02:00
Pankaj Bansal
c022ec039d fsl/mc: Limit the ethernet name to ETH_NAME_LEN
The ethernet name should be within the ETH_NAME_LEN, as this
is the buffer space allocated to ethernet name.

Otherwise, this causes buffer overflow.

Reported-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-08 08:23:49 -07:00
Siva Durga Prasad Paladugu
26026e695a net: zynq_gem: convert to use livetree
This patch updates the zynq gem driver to support livetree.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:23 -05:00
Grygorii Strashko
41080e180c drivers: net: zynq_gem: fix phy dt node setting
Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:23 -05:00
Grygorii Strashko
d4bb981700 drivers: net: cpsw: fix phy dt node setting
Now CPSW driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:23 -05:00
Grygorii Strashko
aadbd97843 net: phy: xilinx: switch to use phy_get_ofnode()
Use PHY API phy_get_ofnode() helper to get PHY DT node.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:22 -05:00
Grygorii Strashko
b8d7ec782f net: phy: dp83867: switch to use phy_get_ofnode()
Use PHY API phy_get_ofnode() helper to get PHY DT node.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:22 -05:00
Grygorii Strashko
eef0b8a930 net: phy: add ofnode node to struct phy_device
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):

- network drivers
	priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
				   priv->interface);
	<-- phydev is connected to dev which is UCLASS_ETH device

	if (priv->phy_of_handle > 0)
		dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
	<-- phydev->dev->node is overwritten by phy-handle DT node

- PHY driver in .config() callback
	int node = dev_of_offset(dev);
	<-- PHY driver uses overwritten dev->node
        const void *fdt = gd->fdt_blob;

	 if (fdtdec_get_bool(fdt, node, "property"))
		...

As result, UCLASS_ETH device can't be used any more for DT accessing.

This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:22 -05:00
Joe Hershberger
05b60ac549 net: phy: Clean up includes of common.h
We want to be able to include some other system headers in phy.h but
that requires us to have included common.h in the top-level first.

Also, common.h includes config.h as the first thing it does, so don't
include it directly.

Series-to: u-boot
Series-cc: Grygorii Strashko <grygorii.strashko@ti.com>
Seried-cc: ti
Series-process-log: sort, uniq
Cover-letter:
Prepare for net: phy: prevent uclass_eth device "node" field overwriting
Prepare for [1] so that it doesn't break the build for a bunch of
boards. There are a number of reasons this series broke the build
but none of them depend on changes in the series, so fix up those
situations ahead of applying that series.

[1] https://patchwork.ozlabs.org/cover/940104/
END
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:22 -05:00
Grygorii Strashko
3ab75cf76e net: phy: dp83867: switch to use ofnode api
Switch to use more generic ofnode API instead of FDT API.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:21 -05:00
Murali Karicheri
63d3192984 net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).

It further advises that if a board has this pin strapped in mode 1 and
mode 2, then bit[7] of Configuration Register 4 (address 0x0031) must
be cleared to 0. This is to ensure proper operation of PHY.

Since it is not possible to detect in software if RX_DV/RX_CTRL pin is
incorrectly strapped, add a device-tree property to advertise this and
allow corrective action in software.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
2018-07-26 14:08:21 -05:00
Chris Packham
fb73107698 net: mvgbe: convert to DM
Add driver model support to the mvgbe driver. As a temporary measure
both DM and non-DM uses are supported. Once all the users have been
converted the non-DM support can be dropped.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:21 -05:00
Chris Packham
e9bf75c9d3 net: mvgbe: prepare for conversion to driver model
Extract some function bodies to helper functions that can be reused in
the DM/non-DM implementations.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:20 -05:00
Joe Hershberger
f40a31e695 sandbox: eth-raw: Add a SIMPLE_BUS to enumerate host interfaces
Ask the OS for each of its interfaces and for each one, bind a U-Boot
device and then probe it. This will allocate the priv data structure
that is then populated.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:19 -05:00
Joe Hershberger
b96ced9cdb sandbox: eth-raw: Make random MAC addresses available to eth-raw
We don't necessarily know how many MAC addresses we'll need, so implement
a ROM read so we always have something valid.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00
Joe Hershberger
c9e2caff85 sandbox: eth-raw: Allow interface to be specified by index
With systemd stable interface names, eth0 will almost never exist.
Instead of using that name in the sandbox.dts, use an index.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-26 14:08:18 -05:00