Commit graph

107 commits

Author SHA1 Message Date
Baruch Siach
6d4d9bea35 MIPS: drop asm/const.h
Commit 86f21c96f4 (mips: Use common _AC macro now.) removed the _AC
definition from const.h. All other macros defined in const.h are not
used anywhere, and there is now no user of this header. Remove this
header.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Baruch Siach
5c8fd32b22 Use _AC and UL macros from linux/const.h
Drop the _AC and UL macros from common.h. Linux headers is the original
source of this macro, so keep its definition in the same header.

Update existing users of these macros to include const.h directly.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-11-20 13:08:15 +01:00
Stefan Roese
4ff942b059 mips: mt76xx: Enable watchdog support
This patch enables and starts the watchdog on the MT7620 platform.
Currently the WD timeout is configured to 60 seconds.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[fixed build error due to missing function prototype arch_misc_init]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-11-18 16:02:22 +01:00
Mario Six
4d9ada54a2 mips: Implement {in, out}_{le, be}_{16, 32, 64} and {in, out}_8
MIPS is the only architecture currently supported by U-Boot that does
not implement any of the in/out register access functions.

To have a interface that is useable across architectures, add the
functions to the MIPS architecture (implemented using the __raw_write
and __raw_read functions).

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-11-14 09:16:27 -08:00
Chris Packham
02df9c5a67 mips: use asm-generic/atomic.h
Make use of asm-generic/atomic.h.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-09-25 21:49:18 -04:00
Stefan Roese
503f6f759c mips: Add arch/mips/include/asm/atomic.h
This is needed for the UBIFS support. The file is a copy of
arch/xtensa/include/asm/atomic.h

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-09-22 21:17:54 +02:00
Masahiro Yamada
3747bdbb2b arch: types.h: factor out fixed width typedefs to int-ll64.h
All architectures have the same definition for s8/16/32/64
and u8/16/32/64.

Factor out the duplicated code into <asm-generic/int-ll64.h>.

BTW, Linux unified the kernel space definition into int-ll64.h
a few years ago as you see in Linux commit 0c79a8e29b5f
("asm/types.h: Remove include/asm-generic/int-l64.h").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-09-10 20:48:16 -04:00
Tom Rini
481ea2e39d mips: au1x00: Remove support for these SoCs
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an
apparent clone of the dbau1x00 platform.  As pb1x00 had no listed
maintainer I am assuming that it is also orphaned.  Remove this platform
and then remove the unused SoC support.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-08-08 13:34:27 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Paul Burton
d8b326976a MIPS: Clear instruction hazards in flush_cache()
When writing code, for example during relocation, we ensure that the
icache has a coherent view of the new instructions with a call to
flush_cache(). This handles the bulk of the work to ensure the new
instructions will execute as expected, however it does not ensure that
the CPU pipeline doesn't already contain instructions taken from a stale
view of the affected memory. This could theoretically be a problem for
relocation, but in practice typically isn't because we sync caches for
enough code after the entry point of the newly written code that by the
time the CPU pipeline might possibly fetch any of it we'll have long ago
written it back & invalidated any stale icache entries. This is however
a problem for shorter regions of code.

In preparation for later patches which write shorter segments of code,
ensure any instruction hazards are cleared by flush_cache() by
introducing & using a new instruction_hazard_barrier() function which
makes use of the jr.hb instruction to clear the hazard.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
2017-11-28 21:59:30 +01:00
Paul Burton
d1cbeafd5e mips: Use asm-generic/io.h
Convert the mips architecture to make use of the new asm-generic/io.h to
provide address mapping functions. As mips actually performs
non-identity mapping between physical & virtual addresses we can't
simply make use of the generic functions, with the exception of being
able to drop our no-op unmap_physmem() and definitions of unused map
flags.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-10-02 21:52:23 -04:00
Paul Burton
703ec9ddf9 MIPS: Stop building position independent code
U-Boot has up until now built with -fpic for the MIPS architecture,
producing position independent code which uses indirection through a
global offset table, making relocation fairly straightforward as it
simply involves patching up GOT entries.

Using -fpic does however have some downsides. The biggest of these is
that generated code is bloated in various ways. For example, function
calls are indirected through the GOT & the t9 register:

  8f998064   lw     t9,-32668(gp)
  0320f809   jalr   t9

Without -fpic the call is simply:

  0f803f01   jal    be00fc04 <puts>

This is more compact & faster (due to the lack of the load & the
dependency the jump has on its result). It is also easier to read &
debug because the disassembly shows what function is being called,
rather than just an offset from gp which would then have to be looked up
in the ELF to discover the target function.

Another disadvantage of -fpic is that each function begins with a
sequence to calculate the value of the gp register, for example:

  3c1c0004   lui    gp,0x4
  279c3384   addiu  gp,gp,13188
  0399e021   addu   gp,gp,t9

Without using -fpic this sequence no longer appears at the start of each
function, reducing code size considerably.

This patch switches U-Boot from building with -fpic to building with
-fno-pic, in order to gain the benefits described above. The cost of
this is an extra step during the build process to extract relocation
data from the ELF & write it into a new .rel section in a compact
format, plus the added complexity of dealing with multiple types of
relocation rather than the single type that applied to the GOT. The
benefit is smaller, cleaner, more debuggable code. The relocate_code()
function is reimplemented in C to handle the new relocation scheme,
which also makes it easier to read & debug.

Taking maltael_defconfig as an example the size of u-boot.bin built
using the Codescape MIPS 2016.05-06 toolchain (gcc 4.9.2, binutils
2.24.90) shrinks from 254KiB to 224KiB.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: u-boot@lists.denx.de
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-07-25 20:44:00 +02:00
Simon Glass
a320acc419 mips: Make u-boot-mips.h a private header
Rather than including this arch-specific header file in common.h, include
it from within mips's u-boot.h header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2017-06-05 11:02:33 -04:00
Tom Rini
86f21c96f4 mips: Use common _AC macro now.
MIPS no longer needs to have its own version of this macro now.

Fixes: 2a6713b09b ("move UL() macro from armv8/mmu.h into common.h")
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-01-10 08:19:26 -05:00
Paul Burton
6fd596a1aa MIPS: Fix map_physmem for cached mappings
map_physmem should return a pointer that can be used by the CPU to
access the given memory - on MIPS simply returning the physical address
as it does prior to this patch doesn't achieve that. Instead return a
pointer to the memory within (c)kseg0, which matches up consistently
with the (c)kseg1 pointer that uncached mappings return via ioremap.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30 16:18:19 +01:00
Marek Vasut
e7e0469c88 mips: Let cache.h be included from assembly source
Add ifdef __ASSEMBLY__ around the function prototype to let cache.h
be included from assembly code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2016-11-30 16:13:17 +01:00
Daniel Schwierzeck
6c59363004 MIPS: add handling for generic and EJTAG exceptions
Add exception handlers for generic and EJTAG exceptions. Most of
the assembly code is imported from Linux kernel and adapted to U-Boot.
The exception vector table will be reserved above the stack before
U-Boot is relocated. The exception handlers will be installed and
activated after relocation in the initr_traps hook function.

Generic exceptions are handled by showing a CPU register dump similar
to Linux kernel. For example:

malta # md 1
00000001:
Ooops:
$ 0   : 00000000 00000000 00000009 00000004
$ 4   : 8ff7e108 00000000 0000003a 00000000
$ 8   : 00000008 00000001 8ff7cd18 00000004
$12   : 00000002 00000000 00000005 0000003a
$16   : 00000004 00000040 00000001 00000001
$20   : 00000000 8fff53c0 00000008 00000004
$24   : ffffffff 8ffdea44
$28   : 90001650 8ff7cd00 00000004 8ffe6818
Hi    : 00000000
Lo    : 00000004
epc   : 8ffe6848 (text bfc28848)
ra    : 8ffe6818 (text bfc28818)
Status: 00000006
Cause : 00000410 (ExcCode 04)
BadVA : 8ff9e928
PrId  : 00019300
 ### ERROR ### Please RESET the board ###

EJTAG exceptions are checked for SDBBP and delegated to the SDBBP handler
if necessary. Otherwise the debug mode will simply be exited. The SDBBP
handler currently prints the contents of registers c0_depc and c0_debug.
This could be extended in the future to handle semi-hosting according to
the MIPS UHI specification.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Tested-by: Paul Burton <paul.burton@imgtec.com>
2016-11-30 16:12:17 +01:00
Daniel Schwierzeck
67588bdade MIPS: add asm-offsets for struct pt_regs
Import asm-offsets.c from kernel to generate offset for struct pt_regs
needed by exception handlers.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:46 +01:00
Daniel Schwierzeck
65d297af7c MIPS: fix iand optimize setup of CP0 registers
Clear cp0 status while preserving implementation specific bits.
Set bits BEV and ERL as the arch specification requires after
a reset or soft-reset exception.

Extend and fix initialization of watch registers. Check if additional
watch register sets are implemented and initialize them too.

Initialize cp0 count as early as possible to get the most
accurate boot timing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-11-30 16:11:46 +01:00
Simon Glass
a0b49bc334 efi: Use asmlinkage for EFIAPI
This is required for x86 and is also correct for ARM (since it is empty).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2016-10-19 09:01:53 +02:00
Masahiro Yamada
4491327d59 Remove arch/${ARCH}/include/asm/errno.h
Unlike Linux, nothing about errno.h is arch-specific in U-Boot.
As you see, all of arch/${ARCH}/include/asm/errno.h is just a
wrapper of <asm-generic/errno.h>.  Actually, U-Boot does not
export headers to user-space, so we just have to care about the
consistency in the U-Boot tree.

Now all of include directives for <asm/errno.h> are gone.
Deprecate <asm/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-09-23 17:56:18 -04:00
Paul Burton
31d36f748c MIPS: Hang if run on a secondary CPU
Some systems are configured such that multiple CPUs begin running from
their reset vector following a system reset. If this occurs then U-Boot
will be run on multiple CPUs simultaneously, which causes all sorts of
issues as the multiple instances of U-Boot clobber each other.

Prevent this from happening by simply hanging with an infinite loop if
we run on a CPU whose ID, as determined by GlobalNumber or EBase.CPUNum
as appropriate, is non-zero.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 17:04:53 +02:00
Paul Burton
7953354b07 MIPS: Join the coherent domain when a CM is present
MIPS Linux expects the bootloader to leave the boot CPU a member of the
coherent domain when running on a system with a CM, and we will need to
do so if we wish to make use of IOCUs to have cache-coherent DMA in
U-Boot (and on some systems there is no choice in that matter). When a
CM is present, join the coherent domain after completing cache
initialisation.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
4baa0ab67d MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.

If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
b2b135d980 MIPS: Map CM Global Control Registers
Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
4f9226b403 MIPS: Preserve Config implementation-defined bits
The coprocessor 0 Config register includes 9 implementation defined
bits, which in some processors do things like enable write combining or
other functionality. We ought not to wipe them to 0 during boot. Rather
than doing so, preserve their value & only clear the bits standardised
by the MIPS architecture.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
8cb4817d0f MIPS: Probe cache line sizes once during boot
Rather than probing the cache line sizes on every call of any cache
maintenance function, probe them once during boot & store the values in
the global data structure for later use. This will reduce the overhead
of the cache maintenance functions, which isn't a big deal yet but
becomes more important once L2 caches which may expose their properties
via coprocessor 2 or the CM are supported.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-09-21 15:04:04 +02:00
Paul Burton
372286217f MIPS: Split I & D cache line size config
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:44:24 +02:00
Daniel Schwierzeck
83b0face8c MIPS: remove dead code from asm/u-boot-mips.h
Those wrappers for linker symbols were once used in the MIPS
specific board.c implementation. Since the migration to generic
board.c, those wrappers are dead code and can be removed.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-31 09:38:11 +02:00
Paul Burton
2e4cc1c5d4 MIPS: Use CPHYSADDR to implement mips32 virt_to_phys
Use CPHYSADDR to implement the virt_to_phys function for converting from
a virtual to a physical address for MIPS32, much as is already done for
MIPS64. This allows for virt_to_phys to work regardless of whether the
address being translated is in kseg0 or kseg1, unlike the previous
subtraction based approach which only worked for addresses in kseg0.
This allows for drivers to provide an address to virt_to_phys without
needing to manually ensure that kseg1 addresses are converted to
equivalent kseg0 addresses first.

This patch is equivalent to this Linux patch currently waiting to be
reviewed & merged:

    https://patchwork.linux-mips.org/patch/12564/

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-05-31 09:38:11 +02:00
Simon Glass
3e085c9946 mips: Drop unused code in u-boot.h
Since generic board init is enabled, this is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-05-27 15:39:53 -04:00
Marek Vasut
1ad3a6fb5b mips: Drop JZ4740 remnants
Remove the remnants of JZ4740 support.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2016-05-26 01:34:14 +02:00
Wills Wang
1d3d0f1f1c mips: add base support for QCA/Atheros ath79 SOCs
This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.

Signed-off-by: Wills Wang <wills.wang@live.com>
2016-05-21 01:25:50 +02:00
Matthias Schiffer
499b847521 MIPS: fix mips_cache fallback without __builtin_mips_cache
The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register
instead.

Fixes: 2b8bcc5a ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-03-09 11:00:40 +01:00
Paul Burton
05e342554e MIPS: Support dynamic I/O port base address
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Paul Burton
8ac493cd65 MIPS: Remove SLOW_DOWN_IO
CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in
the SLOW_DOWN_IO macro. This is done in preparation for changes to
mips_io_port_base which can be avoided in this path by removing it
entirely.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2016-02-01 22:13:25 +01:00
Tom Rini
d6ea6d8876 mips: asm/io.h: Add in <linux/bug.h>
As part of the bug.h / BUILD_BUG_* clean up, this file was missed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-25 18:52:23 -05:00
Daniel Schwierzeck
0e0efb40b8 MIPS: implement bit manipulating I/O accessors
Add support for functions clrbits_X(), setbits_X() and clrsetbits_X()
on MIPS.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
898582bdee MIPS: fix SPDX license identifier in remaining arch header files
Add a SPDX license identifier to MIPS header files where it is
still missing.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
a3ab2ae7f6 MIPS: sync processor and register definitions with linux-4.4
Update definitions for processor, registers as well as assemby
macros.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
23ff8633fd MIPS: sync I/O related header files with linux-4.4
Mainly sync asm/io.h to get a working ioremap() implementation
as well as the full set of I/O accessors. Pull in additional
header files to make this work.

Furthermore port over the directory 'arch/mips/include/asm/mach-generic/'
with contains default definitions for I/O and memory spaces and default
implementations for mapping those spaces. All files in that directory
can be overwritten by a SoC/machine.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
f53830e74e MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFT
Add Kconfig symbol for L1 cache shift like the kernel does.
The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source
for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS.
If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the
cache sizes are automatically detected and ARCH_DMA_MINALIGN
would be set to 128 Bytes.

The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which
corresponds to 32 Bytes. All current MIPS boards already used
that value. While on it, fix the Malta board to use a value of 6
like the kernel port does.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
76ada5f8b7 MIPS: au1x00: move SoC header files to arch/mips/mach-au1x00/include/mach/
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:46 +01:00
Daniel Schwierzeck
5b6f357fe7 MIPS: create .text sub-sections for assembler functions
Put all functions coded in assembly in sub-sections of
section .text. This allows the linker to garbage collect
unused assembly functions too.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Daniel Schwierzeck
113492988b MIPS: fix annotation of _start and relocate_code
Correctly annotate _start and relocate_code as functions to
produce more readable disassembly code generated by objdump.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-01-16 21:06:45 +01:00
Purna Chandra Mandal
1a96780016 MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.
With CONFIG_CMD_GPIO compilation reports error.
common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory
 #include <asm/gpio.h>
                      ^
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-16 21:06:45 +01:00
Fabio Estevam
b810aa1dd1 mips: Use the generic bitops headers
The generic bitops headers are required when calling logarithmic
functions, such as ilog2().

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-11-05 10:52:26 -05:00
Chris Packham
73a4152b25 mips: Use unsigned int when reading c0 registers
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).

Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).

The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.

Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.

Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
2015-08-21 15:22:41 +02:00
Daniel Schwierzeck
b11c5d1dc2 MIPS: change 'extern inline' to 'static inline'
The kernel changed it a long time ago. Also this is now broken
on gcc-5.x.

Reported-by: Andy Kennedy <andy.kennedy@adtran.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2015-07-02 11:29:33 +02:00
Tony Wu
49bbdae318 MIPS: fix missing semicolon in cacheops.h
Fix missing semicolon in cacheops.h introduced in commit
2b8bcc5a2 (MIPS: avoid .set ISA for cache operations)

Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: Paul Burton <paul.burton@imgtec.com>
2015-07-02 11:29:33 +02:00