Commit graph

3695 commits

Author SHA1 Message Date
Chee Hong Ang
eb13dddd2c ARMv8: SError exception handling in PSCI exception vectors
Allow platform vendors to handle SError interrupt exceptions from
ARMv8 PSCI exception vectors by overriding this weak function
'plat_error_handler'.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Chee Hong Ang
c0f3296f83 ARMv8: Add EL3 exception handling for ARMv8's Kconfig
Kconfig option to allow all External Abort and SError exception
taken to EL3.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16 13:34:34 -05:00
Vladimir Zapolskiy
72f6d6b7ea arm: lpc32xx: remove phantom CONFIG_LPC32XX_SDRAM_ config option
The option has never existed and config whitelist script accumulates
it from a comment block, wipe it out from the source code.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2018-10-19 12:56:58 -04:00
Vladimir Zapolskiy
ee54dfea45 arm: lpc32xx: add CONFIG_ARCH_LPC32XX build option
The explicit arch specific build symbol allows to group supported
boards, generalize common config options and it will serve as
a dependency for platform only drivers.

Two related board defconfigs are resynced after the change.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2018-10-19 12:56:58 -04:00
Siva Durga Prasad Paladugu
5860bc16b9 arm64: zynqmp: Add new command for TCM initialization
This patch adds new zynqmp command "zynqmp tcminit mode" to
initialize TCM. TCM needs to be initialized before accessing
to avoid ECC errors. This new command helps to perform
the same. It also makes tcm_init() as global and uses it for
doing the TCM initialization.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Siva Durga Prasad Paladugu
12ad2994a5 arm64: zynqmp: Move TCM initialization to a separate routine
This patch moves TCM initialization to a separate routine to
make it modular and can be reused if required. It also prints
warning message now as it writes to TCM.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16 16:53:24 +02:00
Patrick Delaunay
6180ea7e66 arm: remove prototype for get_timer_masked
The interruption support had be removed for ARM architecture and
the function get_timer_masked() is no more used except in some
the timer.c files.

This patch clean each timer.c which implement this function and
remove the associated prototype in u-boot-arm.h

For timer.c, I don't verify if the weak version of get_timer
(in lib/time.c) can be used

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Patrick Delaunay
aa33fe8695 arm: remove prototype for udelay_masked
The interruption support had be removed for ARM architecture and
the function udelay_masked() is no more used except in some timer.c
files  and have the same content than udelay() or __udelay().

This patch update each timer.c implementing this function and
remove the associated prototype in u-boot-arm.h.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Patrick Delaunay
aad5b4a351 arm: remove prototype for reset_timer_masked
Remove prototype for function only used in one file

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10 13:35:09 -04:00
Tom Rini
27f622d568 Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
 Switch to driver model for SATA on LS1021A and LS1043A.
 Add support for LS1012AFRWY rev C board.
 Enable SMMU for LS1043A.
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Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq

Switch to driver model for eSDHC on Layerscape SoCs including LS1021A,
LS1043A, LS1046A, LS1088A, LS2088A.
Switch to driver model for SATA on LS1021A and LS1043A.
Add support for LS1012AFRWY rev C board.
Enable SMMU for LS1043A.
2018-09-29 11:47:32 -04:00
Ran Wang
26cbc0d663 armv7: ls102xa: Disable QE before enter deep sleep
Otherwise system will hang after executing wfi.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 10:01:28 -07:00
Laurentiu Tudor
dc29a4c177 armv8: ls1043a: add icid setup support
Reuse the existing ICID setup code done for LS1046A smmu enablement
and add the equivalent setup for LS1043A chips.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:58:15 -07:00
Peng Ma
686203737e armv7: fsl: remove sata support
Remove the old implementation in order to enable DM for sata

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:53:03 -07:00
Yinbo Zhu
0fdf696721 armv8/ls1088a/ls2088a: esdhc: Add esdhc clock support
This patch adds esdhc clock support for ls1088a and ls2088a.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:50:26 -07:00
Yinbo Zhu
c3ced8a6ed ppa/fm/qe: use block layer in ppa/fm/qe driver
At present the MMC subsystem maintains its own list of MMC devices.
This cannot work with driver model when CONFIG_BLK is enabled, use
blk_dread to replace previous mmc read interface, use
mmc_get_blk_desc to get the mmc device property.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
[York S: reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27 08:48:51 -07:00
Tom Rini
bbef20d479 Xilinx changes for v2018.11
- Handle BOARD_LATE_INIT via Kconfig
 
 SPL:
 - Enable GZIP for all partitions types(not only for kernel)
 
 ZynqMP:
 - Rearrange pmufw version handling
 - Support newer PMUFW with improved fpga load sequence
 
 Zynq:
 - Cleanup config file
 - Simplify zybo config by enabling option via Kconfig
 
 net:
 - Fix gems max-speed property reading
 - Enable support for fixed-link phys
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Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.11

- Handle BOARD_LATE_INIT via Kconfig

SPL:
- Enable GZIP for all partitions types(not only for kernel)

ZynqMP:
- Rearrange pmufw version handling
- Support newer PMUFW with improved fpga load sequence

Zynq:
- Cleanup config file
- Simplify zybo config by enabling option via Kconfig

net:
- Fix gems max-speed property reading
- Enable support for fixed-link phys
2018-09-27 08:29:10 -04:00
Tom Rini
0ae8dcfef7 Patch queue for efi - 2018-09-26
A lot of goodness in this release. We're *very* close to running the
 UEFI Shell and SCT natively. The only missing piece are HII protocols.
 
   - FAT write support (needed for SCT)
   - improved FAT directory support (needed for SCT)
   - RTC support with QEMU -M virt
   - Sandbox support (run UEFI binaries in Linux - yay)
   - Proper UTF-16 support
   - EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
   - EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
   - Fix window size determination
   - Fix Tegra by explicitly unmapping RAM
   - Clean up handle entanglement
   - Lots of generic code cleanup
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-09-26

A lot of goodness in this release. We're *very* close to running the
UEFI Shell and SCT natively. The only missing piece are HII protocols.

  - FAT write support (needed for SCT)
  - improved FAT directory support (needed for SCT)
  - RTC support with QEMU -M virt
  - Sandbox support (run UEFI binaries in Linux - yay)
  - Proper UTF-16 support
  - EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell)
  - EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell)
  - Fix window size determination
  - Fix Tegra by explicitly unmapping RAM
  - Clean up handle entanglement
  - Lots of generic code cleanup

[trini: Fixup merge conflict in include/configs/qemu-arm.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-26 17:02:46 -04:00
Siva Durga Prasad Paladugu
b94a8271cc arm64: zynqmp: Return pmufw version for zynqmp_pmufw_version()
Modify the zynqmp_pmufw_version() routine to return PMUFW version so
that it can be reused wherever required. Get PMUFW version from PMU
only once at bootup and later just return stored value.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Siva Durga Prasad Paladugu
fe68f2332d arm64: zynqmp: Move PM version related macros to .h
This patch moves the PM version related macros to .h file so that
they can be reused in other files.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26 10:15:00 +02:00
Quentin Schulz
ac47fbee6d arm: spear: enable SSP1, 2 and 3 clocks when SPI controller driver is built
SPI controllers SSP1, 2 and 3 require to enable their respective clocks.
Let's enable them only when the SPI controller driver is built.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-25 21:49:18 -04:00
Stephen Warren
9b5e6396bf efi_loader: simplify ifdefs
Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL
too. This simplifies the conditional.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-23 21:55:29 +02:00
Quentin Schulz
d2d908d258 arm: spear: enable GPIO3 and 4 clocks when the GPIO controller driver is built
There are multiple GPIOs that can be used with the same driver depending
on the CONFIG_GPIO_BASE defined in the controller driver.

GPIO3 and 4 require a clock to be enabled so let's enable them when the
driver is built.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-10 21:19:32 -04:00
Adam Ford
93b283d49f ARM: CPU: arm926ejs: Consolidate cache routines to common file
Four different boards had different options for enabling cache
that were virtually all the same.  This consolidates these
common functions into arch/arm/cpu/arm926ejs/cache.c

This also has the positive side-effect of enabling cache on
the Davinci (da850) boards.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Add mach-at91 to the list of consolidations]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-10 21:19:16 -04:00
Chen-Yu Tsai
792b204798 ARM: Specify aligned address for secure section instead of using attributes
In commit a1274cc94a ("ARM: Page align secure section only when it is
executed in situ"), we used output section attributes (the "ALIGN"
keyword after the colon) to specify the alignment requirements. Using
the constant "COMMONPAGE" there was recently broken in binutils 2.31 [1].

Binutils maintainer Alan Modra suggested the former method would still
work. Since both methods achieve the same result, this patch does just
that. This fixes the "reboot after bootm" issue we've been seeing on
sunxi when booting non-secure.

  [1] https://sourceware.org/bugzilla/show_bug.cgi?id=23571

Suggested-by: Alan Modra <amodra@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-09-07 09:11:42 -04:00
York Sun
50f566d6ee armv8: fsl-layerscape: Update README.falcon for compression
Update README.falcon to use "none" for compression property for
ramdisk image to avoid being uncompressed upon loading.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-08-23 08:17:35 -07:00
Ran Wang
9add5a4b75 armv8: layerscape: Enable EHCI access for LS1012A
Program Central Security Unit (CSU) to grant access to USB 2.0
controller.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: rewrite commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:37:39 -07:00
Laurentiu Tudor
5651f438f8 armv8: ls1046a: setup SEC ICIDs and fix up device tree
Add support for SEC ICID configuration and apply it for ls1046a.
Also add code to make the necessary device tree fixups.

Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:46 -07:00
Laurentiu Tudor
b50ff5e1b6 armv8: ls1046a: setup fman ports ICIDs and device tree
Add support for ICID setting of fman ports and the required device
tree fixups.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:42 -07:00
Laurentiu Tudor
599a97d49c armv8: ls1046a: add icid setup for qman portals
Add support for ICID setting of qman portals and the required device
tree fixups. Also fix an endiness issue in portal setup code.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:36 -07:00
Laurentiu Tudor
3cb4fe65f9 armv8: ls1046a: initial icid setup support
Add infrastructure for ICID setup and device tree fixup on ARM
platforms. This include basic ICID setup for several devices.

Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-10 10:35:33 -07:00
Brendan Shanks
e784cf1bf2 arm: ls102xa: Fix RGMII phy-connection-type FDT fixup
In ft_fixup_enet_phy_connect_type(), use strlen() instead of sizeof()
on the pointer result of phy_string_for_interface(). sizeof() was
returning the size of the pointer (4 bytes), resulting in the
phy-connection-type being set to "rgmi" rather than "rgmii-id".

Signed-off-by: Brendan Shanks <brendan.shanks@teradek.com>
Cc: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-08-07 14:42:15 -07:00
Andre Przywara
1416e2d225 armv8: make SPL exception vectors optional
Even though the exception vector table is a fundamental part of the ARM
architecture, U-Boot mostly does not make real use of it, except when
crash dumping. But having it in takes up quite some space, partly due to
the architectural alignment requirement of 2KB. Since we don't take special
care of that, the compiler adds a more or less random amount of padding
space, which increases the image size quite a bit, especially for the SPL.

On a typical Allwinner build this is around 1.5KB of padding, plus 1KB
for the vector table (mostly padding space again), then some extra code
to do the actual handling. This amounts to almost 10% of the maximum image
size, which is quite a lot for a pure debugging feature.

Add a Kconfig symbol to allow the exception vector table to be left out
of the build for the SPL.
For now this is "default y" for everyone, but specific defconfigs,
platforms or .config files can opt out here at will, to mitigate the code
size pressure we see for some SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Andre Przywara
15b6184971 armv8: Reduce exception handling code
The arm64 exception handling code is quite big, mostly due to
architectural alignment requirements. Each exception entry spans 32
instructions, which sounds generous, but is too small to fit all of the
save/branch/restore code in there. So at the moment we use only four
instructions, branching into shared save and restore routines.
To not leave the space for those remaining 28 instructions wasted, let's
split the save and restore routines and stuff them into the gaps.
This saves about 250 bytes of code, which is helpful for those tight
SPLs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-08-03 19:53:54 -04:00
Tom Rini
406fd7e207 Patch queue for efi - 2018-07-25
Highlights this time:
 
   - Many small fixes to improve spec compatibility (found by SCT)
   - Almost enough to run with sandbox target
   - GetTime() improvements
   - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
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Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

Patch queue for efi - 2018-07-25

Highlights this time:

  - Many small fixes to improve spec compatibility (found by SCT)
  - Almost enough to run with sandbox target
  - GetTime() improvements
  - Enable EFI_LOADER and HYP entry on ARMv7 with NONSEC=y
2018-07-30 16:02:29 -04:00
Michal Simek
58008cbab5 Kconfig: Sort bool, default, select and imply options
Another round of sorting Kconfig entries aplhabetically.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-30 07:18:48 -04:00
Tom Rini
0e8a8a3110 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-07-27 13:09:30 -04:00
Joe Hershberger
9cce566321 arm: Prevent redefinition error in fsl-layerscape
The include/phy.h will start including dm.h, which pulls in
linux/compat.h after the attempted redefinition in
arch/arm/include/asm/armv8/mmu.h, so move this include to allow
redefinition.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-26 14:08:21 -05:00
York Sun
038b965c2b armv8: ls1046ardb: Add falcon mode for for QSPI boot
A new defconfig is introduced to support SPL boot from QSPI NOR
flash. This is to support falcon mode for faster booting into
Linux.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 11:51:23 -07:00
York Sun
9960609275 armv8: layerscape: spl: Initialize QSPI AHB for QSPI boot
To get full access of QSPI space, initialize AHB interface.

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Yuantian Tang
ed167eb1c7 armv8: fsl: remove sata support
Remove the old implementation in order to enable DM for sata.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
York Sun
61ab8aac60 armv8: layerscape: Enabled I-cache for SPL boot
Enable I-cache for SPL boot to boost performance. Earlier MMU was
enabled only for LS2080A and has since been dropped by commit
f539c8a4a7 ("armv8: ls2080a: Drop early MMU for SPL build").

Signed-off-by: York Sun <york.sun@nxp.com>
2018-07-26 10:59:35 -07:00
Alexander Graf
7e21fbca26 efi_loader: Rename sections to allow for implicit data
Some times gcc may generate data that is then used within code that may
be part of an efi runtime section. That data could be jump tables,
constants or strings.

In order to make sure we catch these, we need to ensure that gcc emits
them into a section that we can relocate together with all the other
efi runtime bits. This only works if the -ffunction-sections and
-fdata-sections flags are passed and the efi runtime functions are
in a section that starts with ".text".

Up to now we had all efi runtime bits in sections that did not
interfere with the normal section naming scheme, but this forces
us to do so. Hence we need to move the efi_loader text/data/rodata
sections before the global *(.text*) catch-all section.

With this patch in place, we should hopefully have an easier time
to extend the efi runtime functionality in the future.

Signed-off-by: Alexander Graf <agraf@suse.de>
[agraf: Fix x86_64 breakage]
2018-07-25 14:57:44 +02:00
Mark Kettenis
d32e86bde8 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is supported
ARMV7_LPAE is required in order to enable the MMU in HYP mode.
And we really want to enable the MMU in HYP mode such that we can
enable the the caches.  Otherwise U-Boot code (such as the EFI
implementation) that runs in HYP mode will run at a snils pace.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Mark Kettenis
907ee2945e ARM: HYP/non-sec: migrate stack
The current code that switches into HYP mode doesn't bother to set
up a stack for HYP mode.  This doesn't work for EFI applications
as they expect a usable stack.  Fix this by migrating the stack
pointer from SP_svc to SP_hyp while in Monitor mode.
This restores the stack pointer when we drop into HYP mode.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-07-25 14:57:43 +02:00
Stefan Agner
77fcc2cc90 ARM: PSCI: initialize stack pointer on secondary CPUs
A proper stack is required to safely use C code in psci_arch_cpu_entry.

Fixes: 486daaa618 ("arm: psci: add a weak function psci_arch_cpu_entry")
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Patrick DELAUNAY <Patrick.delaunay@st.com>
Tested-by: Patrick DELAUNAY <Patrick.delaunay@st.com>
2018-07-23 10:53:12 +02:00
Tom Rini
4ac5df4b41 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-07-03 23:09:34 -04:00
Andre Przywara
be0d217952 arm: timer: sunxi: add Allwinner timer erratum workaround
The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.

Fixes: 5ff8e54888 ("sunxi: improve throughput
in the sunxi_mmc driver")

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
2018-07-03 22:00:00 +05:30
Andre Przywara
38651588d3 arm: timer: factor out FSL arch timer erratum workaround
At the moment we have the workaround for the Freescale arch timer
erratum A-008585 merged into the generic timer_read_counter() routine.
Split those two up, so that we can add other errata workaround more
easily. Also add an explaining comment on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
2018-07-03 21:59:46 +05:30
Nishanth Menon
c2ca3fdfb9 ARM: Introduce ability to enable invalidate of BTB with ICIALLU on Cortex-A15 for CVE-2017-5715
As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB)
needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to
be done unconditionally for Cortex-A15 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.

NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
   provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the
   right locations.
c) This workaround applies to only the boot processor. It is important
   to apply workaround as necessary (context-save-restore) around low
   power context loss OR additional processors as necessary in either
   firmware support OR elsewhere in OS.

[1] https://developer.arm.com/support/security-update
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Andre Przywara <Andre.Przywara@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-29 11:30:39 -04:00
Nishanth Menon
7b37a9c732 ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for CVE-2017-5715
As recommended by Arm in [1], IBE[2] has to be enabled unconditionally
for BPIALL to be functional on Cortex-A8 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.

NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
   provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the right
   locations.
c) This workaround applies to only the boot processor. It is important
   to apply workaround as necessary (context-save-restore) around low
   power context loss OR additional processors as necessary in either
   firmware support OR elsewhere in OS.

[1] https://developer.arm.com/support/security-update
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Andre Przywara <Andre.Przywara@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-29 11:30:39 -04:00