Commit graph

922 commits

Author SHA1 Message Date
Simon Glass
911954859d dm: Use dm_scan_fdt_dev() directly where possible
Quite a few places have a bind() method which just calls dm_scan_fdt_dev().
We may as well call dm_scan_fdt_dev() directly. Update the code to do this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27 14:15:54 -06:00
Simon Glass
2e3f1ff63f dm: Convert users from dm_scan_fdt_node() to dm_scan_fdt_dev()
This new function is more convenient for callers, and handles pre-relocation
situations automatically.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-07-27 14:15:07 -06:00
Tom Rini
b8e599746c Merge branch 'master' of git://git.denx.de/u-boot-x86 2016-07-12 08:15:17 -04:00
Simon Glass
9532fe3b40 x86: link: Correct a failure in DRAM init
With the change to set up pinctrl after relocation, link fails to boot. Add
a special case in the link code to handle this.

Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r())

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-07-12 13:59:45 +08:00
George McCollister
215099a522 x86: Add Advantech SOM-DB5800/SOM-6867 support
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.

Currently supported:
 - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on
   SOM-DB5800.
 - 4x USB 2.0 (EHCI)
 - Video
 - SATA
 - Ethernet
 - PCIe
 - Realtek ALC892 HD Audio
   Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO
   HDA_SDI0 is set in DT to enable HD Audio codec.
   Pin defaults for codec pin complexs are not changed.

Not supported:
 - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500)
 - USB 3.0 (XHCI)
 - TPM

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-07-12 13:46:01 +08:00
Bin Meng
3ff11aaa50 x86: baytrail: acpi: Hide internal UART per GNVS setting
If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
79c2c257cf x86: acpi: Pack global NVS into ACPI table
Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
cf7108b320 x86: quark: Introduce ACPI global NVS
This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
2047390abc x86: baytrail: Introduce ACPI global NVS
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
d9703a0725 x86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UART
For any FSP-enabled boards that want to enable debug UART support,
setup_internal_uart() will be called, but this API is only available
on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Bin Meng
377656b2cc x86: baytrail: Introduce a Kconfig option for the internal UART
There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.

So far BayleyBay and MinnowMax boards are using internal UART as
the U-Boot console, enable this on these two boards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-07-12 13:46:01 +08:00
Simon Glass
6cd2602d61 x86: fdt: Drop the unused compatible strings in fdtdec
We have drivers for several more devices now, so drop the strings which are
no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-07-11 14:06:44 -06:00
Bin Meng
ff6e156966 x86: coreboot: Remove the dummy pch driver
There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-29 10:08:15 +08:00
Bin Meng
d8906c1f3f x86: Probe pinctrl driver in cpu_init_r()
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

 - Pin's PADs only gets configured when GPIO driver is probed, which
   is not done by default. This leaves the board in a partially
   functional state as we must initialize PADs correctly to get
   perepherals fully working.
 - The probe routine of pinctrl driver is called multiple times, as
   normally there are multiple GPIO controllers. It should really
   be called just once.

Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
2016-06-12 12:19:35 +08:00
Bin Meng
f7a01e4848 x86: baytrail: Configure card detect pin of the SD controller
As of today, the latest version FSP (gold4) for BayTrail misses the
PAD configuration of the SD controller's Card Detect signal. The
default PAD value for the CD pin sets the pin to work in GPIO mode,
which causes card detect status cannot be reflected by the Present
State register in the SD controller (bit 16 & bit 18 are always zero).

Add a configuration for this pin in the pinctrl node.

Note I've checked the PAD configuration for all the pins in all the
3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get
initialized to correct mode by FSP. With fsp,emmc-boot-mode set to
2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set
fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3
which is correct according to datasheet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12 12:19:35 +08:00
Bin Meng
58d1fedb1f x86: baytrail: Change fsp, emmc-boot-mode to "auto"
At present all BayTrail boards configure fsp,emmc-boot-mode to 2,
which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1
only shows up on some early stepping silicon of BayTrail SoC.
Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP
provides a config option fsp,emmc-boot-mode which tells FSP which
eMMC controller it initializes. Instead of hardcoded to 2, now
we change it to 1 which means "auto".

With this change, MinnowMax board (with a D0 stepping BayTrail SoC)
can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot
'pci' command.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12 12:19:35 +08:00
Bin Meng
e264e3cc5b x86: baytrail: Add 'reg' property in the pinctrl node
Without a 'reg' property, pinctrl driver probe routine fails in
its pre_probe() with a return value of -EINVAL.

Add 'reg' property for all BayTrail boards. Note for BayleyBay,
the pinctrl node is newly added.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12 12:19:35 +08:00
George McCollister
8a1a7595cf x86: acpi: Fix madt lapic generation
An accumulated length was incorrectly added to current each pass
through the loop. On system with more than 2 cores this caused a
corrupt MADT to be generated.

Signed-off-by: George McCollister <george.mccollister@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-06-12 12:19:35 +08:00
Bin Meng
d3d664725b x86: baytrail: acpi: Fix I/O APIC ID in the MADT table
So far this is hardcoded to 2, but it should really be read
from the I/O APIC register.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
7ee371063f x86: quark: Generate ACPI FADT/MADT tables
Generate quark platform-specific FADT/MADT tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
48cf8b8346 x86: quark: Add platform ASL files
This adds basic quark platform ASL files. They are intended to be
included in dsdt.asl of any board that is based on this platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
ec37913221 x86: quark: Prepare device.h for inclusion by ASL
There is a device.h for quark on-chip devices, mainly for definitions
of internal PCI device numbers, but it's not ready to be included by
ASL files. Update to use hex numbers for PCI dev and __ASSEMBLY__.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
3498cc9775 x86: acpi: Make irqroute.asl common
The irqroute.asl file is already common enough to all x86 platforms.
Platform ASL files need only provide a irqroute.h to describe how
internal PCI devices and PCIe downstream port devices' INTx pins are
routed to which PIRQ pin.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
0d71511a2a x86: acpi: Create a common irqlinks ASL file
Move the irqlinks.asl file currently in the BayTrail directory to
a common place to be shared among all x86 platforms. As the PIRQ
routing control programming interface is common to Intel chipsets,
leave the common part in the common file, and move the platform
specific part to the platform files.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-30 10:21:12 +08:00
Bin Meng
4cdce9f5b4 x86: Switch to use SMBIOS Kconfig options when writing SMBIOS tables
Make use of the newly added Kconfig options of board manufacturer
and product name to write SMBIOS tables.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:42 +08:00
Bin Meng
5ce378cfcf x86: kconfig: Add two options for SMBIOS manufacturer and product name
This introduces two Kconfig options to be used by SMBIOS tables:
board manufacturer and product name.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:42 +08:00
Bin Meng
b813ea9a14 x86: broadwell: Correct I/O APIC ID
Currently ID 2 is assgined to broadwell I/O APIC, however per
chromebook_samus.dts 2 is the core#2 LAPIC ID. Now we change
I/O APIC ID to 4 to avoid conflict.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:42 +08:00
Bin Meng
911d6f6932 x86: quark: Assign a unique I/O APIC ID
After power-on, both LAPIC and I/O APIC appear with the same APIC ID
zero, which creates an ID conflict. When generating MP table, U-Boot
reports zero as the LAPIC ID in the processor entry, and zero as the
I/O APIC ID in the I/O APIC as well as the I/O interrupt assignment
entries. Such MP table confuses Linux kernel and finally a kernel
panic is seen during boot:

  BUG: unable to handle kernel paging request at ffff9000
  IP: [<c101d462>] native_io_apic_write+0x22/0x30
  *pdpt = 00000000014fb001 *pde = 00000000014ff067 *pte = 0000000000000000
  Oops: 0002 [#1]
  Modules linked in:
  Pid: 1, comm: swapper Tainted: G        W    3.8.7 #3 intel galileo/galileo
  EIP: 0060:[<c101d462>] EFLAGS: 00010086 CPU: 0
  EIP is at native_io_apic_write+0x22/0x30
  ...
  Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:42 +08:00
Bin Meng
e2126711af x86: Call lapic_setup() in interrupt_init()
Let's configure LAPIC in a common place - interrupt_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
aaaa55751a x86: Remove SMP limitation in lapic_setup()
At present LAPIC is enabled and configured as virtual wire mode
in lapic_setup() only when CONFIG_SMP is on. This limitation is
however not necessary as for uniprocessor this is still needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
3299be2479 x86: Don't touch IA32_APIC_BASE MSR on Intel Quark
Intel Quark processor core provides an integrated Local APIC but
does not support the IA32_APIC_BASE MSR. As a result, the Local
APIC is always globally enabled and the Local APIC base address
is fixed at 0xfee00000. Attempting to access the IA32_APIC_BASE
MSR causes a general protection fault.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
0ac8d5e552 x86: galileo: Enable CPU driver
Add a cpu node in the device tree and enable CPU driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:27:41 +08:00
Bin Meng
bab4b96166 x86: Use latest microcode for all BayTrail boards
Update board device tree to include latest microcode, and remove
the old no longer needed microcode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2016-05-23 15:26:46 +08:00
Bin Meng
c88f508f69 x86: baytrail: Update to latest microcode
Update BayTrail microcde to rev 325 (for CPUID 30673), rev 907
(for CPUID 30679).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:24:24 +08:00
Bin Meng
5c60a3abde x86: Add some notes for MRC cache with Intel FSP
MRC cache relies on Intel FSP to produce a special GUID that
contains the MRC cache data. Add such information in the
CONFIG_ENABLE_MRC_CACHE help entry.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
7bfe0da4d2 x86: baytrail: Add GPIO ASL description
Since BayTrail, Intel starts to use new GPIO IPs in their chipset.
This adds the GPIO ASL, so that OS can load corresponding drivers
for it. On Linux, this is BayTrail pinctrl driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
fa427438bd x86: baytrail: Add internal UART ASL description
BayTrail integrates an internal ns15550 compatible UART (PNP0501).
Its IRQ is hardwired to IRQ3 in old revision chipset, but in newer
revision one IRQ4 is being used for ISA compatibility. Handle this
correctly in the ASL file.

Linux does not need this ASL, but Windows need this to correctly
discover a COM port existing in the system so that Windows can
show it in the 'Device Manager' window, and expose this COM port
to any terminal emulation application.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
10fcabed88 x86: acpi: Remove header length check when writing tables
Before moving 'current' pointer during ACPI table writing, we always
check the table length to see if it is larger than the table header.
Since our purpose is to generate valid tables, the check logic is
always true, which can be avoided.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
17b63c80bf x86: acpi: Remove the unnecessary checksum calculation of DSDT
The generated AmlCode[] from IASL already has the calculated DSDT
table checksum in place. No need for us to calculate it again.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
6aef68dc36 x86: acpi: Switch to ACPI mode by ourselves instead of requested by OSPM
Per ACPI spec, during ACPI OS initialization, OSPM can determine
that the ACPI hardware registers are owned by SMI (by way of the
SCI_EN bit in the PM1_CNT register), in which case the ACPI OS
issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit
effectively tracks the ownership of the ACPI hardware registers.

However since U-Boot does not support SMI, we report all 3 fields
in FADT (SMI_CMD, ACPI_ENABLE, ACPI_DISABLE) as zero, by following
the spec who says: these fields are reserved and must be zero on
system that does not support System Management mode.

U-Boot seems to behave in a correct way that the ACPI spec allows,
at least Linux does not complain, but apparently Windows does not
think so. During Windows bring up debugging, it is observed that
even these 3 fields are zero, Windows are still trying to issue SMI
with hardcoded SMI port address and commands, and expecting SCI_EN
to be changed by the firmware. Eventually Windows gives us a BSOD
(Blue Screen of Death) saying ACPI_BIOS_ERROR and refuses to start.

To fix this, turn on the SCI_EN bit by ourselves. With this patch,
now U-Boot can install and boot Windows 8.1/10 successfully with
the help of SeaBIOS using legacy interface (non-UEFI mode).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
644a76742c x86: Use high_table_malloc() for tables passing to SeaBIOS
Now that we already reserved high memory for configuration tables,
call high_table_malloc() to allocate tables from the region.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
d19c90747d x86: Reserve configuration tables in high memory
When SeaBIOS is on, reserve configuration tables in reserve_arch().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
0c2b7eef97 x86: Unify reserve_arch() for all x86 boards
Instead of asking each platform to provide reserve_arch(),
supply it in arch/x86/cpu/cpu.c in a unified way.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
789b6dcecc x86: Prepare configuration tables in dedicated high memory region
Currently when CONFIG_SEABIOS is on, U-Boot allocates configuration
tables via normal malloc(). To simplify, use a dedicated memory
region which is reserved on the stack before relocation for this
purpose. Add functions for reserve and malloc.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
548344912f x86: Compile coreboot_table.c only for SeaBIOS
coreboot_table.c only needs to be built when SeaBIOS is used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
10d569ea1a x86: Fix up PIRQ routing table checksum earlier
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIOS case, when we write the table for the second time, the
checksum will be fixed up to zero per the checksum algorithm, which
is caused by the checksum field not being zero before fix up, since
the checksum has already been calculated in the first run.

To fix this, move the checksum fixup to create_pirq_routing_table(),
so that copy_pirq_routing_table() only does what its function name
suggests: copy the table to somewhere else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Bin Meng
1e2f7b9e8e x86: Call board_final_cleanup() in last_stage_init()
At present board_final_cleanup() is called before booting a Linux
kernel. This actually needs to be done before booting anything,
like SeaBIOS, VxWorks or Windows.

Move the call to last_stage_init() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-23 15:18:00 +08:00
Miao Yan
494ec0d093 x86: qemu: rename qemu/acpi_table.c
Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved
to qfw core, this file only contains code for installing e820 table.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
eece493a7a cmd: qfw: bring ACPI generation code into qfw core
Loading ACPI table from QEMU's fw_cfg interface is not x86 specific
(ARM64 may also make use of it). So move the code to common place.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00
Miao Yan
1868659002 cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]
Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-05-23 15:18:00 +08:00