Commit graph

43121 commits

Author SHA1 Message Date
Jean-Jacques Hiblot
33a5e2c5e7 dra7: dtsi: mark ocp2scp bus compatible with "simple-bus"
This is needed to probe devices under that bus such as the SATA PHY.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Jean-Jacques Hiblot
982082d9ce drivers: phy: add PIPE3 phy driver
This phy is found on omap platforms with sata capabilities.
Except for the part related to the DM and the PHY framework, the code is
basically a copy paste from arch/arm/mach-omap2/pipe3-phy.c

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Jean-Jacques Hiblot
86322f5982 dm: test: Add tests for the generic PHY uclass
Those tests check:
- the ability for a phy-user to get a phy based on its name or its index
- the ability of a phy device (provider) to manage multiple ports
- the ability to perform operations on the phy (init,deinit,on,off)
- the behavior of the uclass when optional operations are not implemented

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Jean-Jacques Hiblot
72e5016f87 drivers: phy: add generic PHY framework
The PHY framework provides a set of APIs to control a PHY. This API is
derived from the linux version of the generic PHY framework.
Currently the API supports init(), deinit(), power_on, power_off() and
reset(). The framework provides a way to get a reference to a phy from the
device-tree.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Jean-Jacques Hiblot
d52063b84f scsi: dm: split scsi_scan()
The DM version of scsi_scan() is becoming a bit long, it can be split:
scsi_scan() iterates over the IDs and LUNs and for each id/lun pair calls
do_scsi_scan_one() to do the work of:
 - detecting an attached drive
 - creating the associated block device if a drive is found.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
eaa59b3404 board: at91sam9263ek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
bbd76227dc board: at91sam9263ek: Clean up code
Because the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
0b8908f9c3 configs: at91sam9263ek: Update for DT and DM support
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
84a9b80dba board: at91sam9rlek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
104c752f84 board: at91sam9rlek: Clean up code
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
2011dca2c1 configs: at91sam9rlek: Update for DT and DM support
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
2510be1d21 board: at91sam9260ek/9g20ek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
c97c2eb1fe board: at91sam9260ek: Clean up code
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
83f1c2ef30 configs: at91sam9260ek/9g20ek: Update for DT and DM
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
6a991af2d1 board: at91sam9m10g45ek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
e95a29e4e5 board: at91sam9m10g45ek: Clean up code
Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:16 -06:00
Wenyou Yang
59b37122b1 configs: at91sam9m10g45ek: Update to support DM/DT
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
c1868adf64 board: at91sam9n12ek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
adc6b2863e board: at91sam9n12ek: Clean up code
Since the introduction of the pinctrl and clk driver and the device
tree files, remove unneeded related code from the board file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
0ab5433da2 configs: at91sam9n12ek: Update for DT and DM support
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
9daf89cb68 board: at91sam9x5ek: Enable early debug UART
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
154de5ad0e board: at91sam9x5ek: Clean up code
Since the introduction of the pinctrl and clock driver and the device
tree files, remove unneeded hard coded related code from the board
file.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
74631b69d6 configs: at91sam9x5ek: Update to support DM/DT
Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
6cb2a7fe81 ARM: dts: at91: Add dts files for at91sam9263ek
The device tree source files of at91sam9263ek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
1e315a356b ARM: dts: at91: Add dts files for at91sam9rlek
The device tree source files of at91sam9rlek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
627e41f125 ARM: dts: at91: Add dts files for at91sam9260ek/9g20ek
The device tree source files of at91sam9g20ek and at91sam9260ek
boards are copied from the Linux v4.10, do the changes below.
 - Fix the build error for the usb0 node.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Add the clk pinctrl of the mmc0 node.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
eb6f87cc07 ARM: dts: at91: Add dts files for at91sam9m10g45ek
The device tree source files of at91sam9m10g45ek boards are copied
from the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property to determine which nodes
   are used by the board_init_f stage.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
cd339347b9 ARM: dts: at91: Add dts files for at91sam9n12ek
The device tree source files of at91sam9n12ek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Change the compatible of the spi flash to "spi-flash".
 - Add the spi0 aliases.
 - Fix the pinctrl-names of mmc0 node.
 - Add the "u-boot,dm-pre-reloc" property to determine which nodes
   are used by the board_init_f stage.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
25e88d406e ARM: dts: at91: Add dts files for at91sam9x5ek
The device tree source files of at91sam9x5ek board are copied from
the Linux v4.10, do the changes below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property to determine which nodes
   are used by the board_init_f stage.
 - Change the compatible of the spi flash to "spi-flash".
 - Add the spi0 aliases.
 - Fix the compilation warnings.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
f8b7fff1d5 serial: atmel_usart: Add clk support
Add the clock support.
Note that the clock handling of the DBGU peripheral is different
from the USART.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
5f29e79915 serial: atmel_usart: Fix early debug not work in SPL
Add the uart init function to be used on both probe and the early
debug uart init. For the latter, the input clock should be from
CONFIG_DEBUG_UART_CLOCK.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
3fea809b42 clk: at91: Align the at91 pmc's compatibles
Align the at91 pmc's compatibles with kernel.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
a9513d47dc clk: at91: Align clk-master compatibles with kernel
Add the compatible "atmel,at91rm9200-clk-master" to align with
the kernel.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
bb1adf2943 clk: at91: Enhance the peripheral clock
Enhance the peripheral clock to support both at9sam9x5's and
at91rm9200's peripheral clock via the different compatibles.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
7546025341 net: macb: Align the compatibles with kernel
Add the compatibles to align with the kernel.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
1870d4d7bd net: macb: Add remove callback
To avoid the failure of mdio_register(), add the remove callback
to unregister the mii_dev when removing the ethernet device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fixed up unused variable warning, e.g. for gurnard:
Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-09 12:14:15 -06:00
Wenyou Yang
1c0ac8222a configs: sama5d3xek: add default config for CMP board
The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rails. The board is mainly used to measure the power
consumption. As all those changes are done in at91bootstrap,
in U-Boot, only use another device tree file, no code needed
to change.

As there is additional power consumption when enbling the USB
Host and USB device, for the power consumption measurement
intention, disable the USB host and device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
0d00f9b6c1 board: sama5d4ek: fix DD2 configuration
Fix the DDR2 configuration to make SPL work.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
62904b7346 configs: sama5d2_xplained: update for SPL
Enable config options to support the SPL, increase the malloc
memory size for the SPL and board_init_f stage and increase
the memory space for the SPL binary.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
5521d9e9e7 board: sama5d2_xplained: remove unnecessary header files
Remove the unnecessary header files.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
ed03b1ba3c board: sama5d2_xplained: remove uart1 init
Due to the pin configuration and clock enabling is handling by the
driver, remove the unneeded hardcode uart1 init during
board_early_init_f stage.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
a66e4d00df board: sama5d2_xplained: clean up macb init code
Because the MACB driver supports the driver model and device tree,
the pins configuration and clock enabling are handled by the
pinctrl driver and clock driver, remove this hardcoded init code.

The USB Ether init code is removed as well.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
d4ce9e7bbf configs: sama5d2_xplained: enable CONFIG_DM_ETH
Enable CONFIG_DM_ETH to make MACB to support driver model.

Because the USB Ether doesn't support driver model so far,
remove this feature.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
4529ee3bc5 ARM: dts: sama5d2_xplained: update for SPL
Add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Wenyou Yang
20bb165c1f ARM: dts: sama5d2: add clock property for uart1 node
Add clock property for uart1 node.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
2017-05-09 12:14:15 -06:00
Tom Rini
85ea850976 p1_p2_rdb: Fix unused variable warning
With gcc-6 we see a warning that sysclk_tbl is defined but unused, so
remove it.

Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-09 09:11:04 -04:00
Maxim Sloyko
78df5e1ed0 dm: Update Simple Watchdog uclass
- Remove "probe" function from sandbox wdt driver
- Fix include order

Fixes: 0753bc2d30 ("dm: Simple Watchdog uclass")
Signed-off-by: Maxim Sloyko <maxims@google.com>
[trini: Create as the delta between v1 (applied) and v2 (should have
 applied)].
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-09 09:08:07 -04:00
Tom Rini
2f92629112 Merge branch 'next' of git://git.denx.de/u-boot-spi 2017-05-08 15:44:52 -04:00
Tom Rini
a6d4cd4778 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2017-05-08 15:44:44 -04:00
Lokesh Vutla
ee3c6532be ARM: keystone2: Add support for getting external clock dynamically
One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2017-05-08 12:34:29 -04:00