With commit 06985289d4 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.
To fix this issue, this patch now removes the old workaround and selects
CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the
complete malloc area is initialized with zeros (cache lines are touched).
Testing has shown that this also fixes the issue on the MT7688 boards.
Signed-off-by: Stefan Roese <sr@denx.de>
Suggested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
because they do not share the same lowlevel codes.
Dependencies of four drivers are changed to SOC_MT7628 as these drivers
are only used by MT7628.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Add initial support for the Ingenic JZ47xx MIPS SoC.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This family of SoCs are found in the Microsemi Switches solution and have
already a support in the linux kernel.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
It has been noticed, that sometimes the d-cache is not in a
"clean-state" when U-Boot is running on MT7688. This was detected when
using the ethernet driver (which uses d-cache) and a TFTP command does
not complete. Flushing the complete d-cache (again?) here seems to fix
this issue.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch enables and starts the watchdog on the MT7620 platform.
Currently the WD timeout is configured to 60 seconds.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
[fixed build error due to missing function prototype arch_misc_init]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Imply DM_ETH and DM_GPIO for ARCH_MT7620, as this platform now supports
ethernet and GPIO as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Currently the size of the relocation table will be shrunk
to the actual size needed. Although this gives a maximal
space saving, it messes up the _end symbol. This breaks
features like appended DTBs because the _end symbol doesn't
point to the real end of the U-Boot binary.
Remove the size shrinking and make the size of the relocation
table fixed but configurable. This follows the Linux approach
and the user can adjust the size to his needs.
Also rename the relocation table section from .rel to .data.reloc
to follow the Linux approach and to avoid ambiguities with the
.rel.* sections added by the linker.
Reported-by: Lars Povlsen <lars.povlsen@microsemi.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds the necessary sysreset DT node and enables the required
drivers via Kconfig.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of
the code is copied from the MediaTek GitHub repository:
https://github.com/MediaTek-Labs/linkit-smart-uboot.git
The mt7628a.dtsi file is imported from Linux v4.17.
Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway
both based on the MT7688 will be added in further patches.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Some MIPS systems store some board-specific boot configuration
in the U-Boot binary at offset 0x10. This is used by Malta boards
and by Lantiq/Intel SoC's when booting from parallel NOR flash.
Convert the hard-coded values to Kconfig options to remove such
board-specific stuff out of the generic start.S code. This also
deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The only platform left for the AU1x00 SoCs was the pb1x00 platform, an
apparent clone of the dbau1x00 platform. As pb1x00 had no listed
maintainer I am assuming that it is also orphaned. Remove this platform
and then remove the unused SoC support.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This platform has been marked as orphan since June of 2016 and should
have been removed some time ago. Do so now.
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
CMD_DM is used for debug purpose and it shouldn't be enabled by default
via Kconfig. Unfortunately this is in the tree for quite a long time
that's why solution is to use imply DM for all targets which are
enabling DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Fix Kconfig bool, default, select and imply options to be
alphabetically sorted.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
At present we support multiple environment drivers but there is not way to
select between them at run time. Also settings related to the position and
size of the environment area are global (i.e. apply to all locations).
Until these limitations are removed we cannot really support more than one
environment location. Adjust the location to be a choice so that only one
can be selected. By default the environment is 'nowhere', meaning that the
environment exists only in memory and cannot be saved.
Also expand the help for the 'nowhere' option and move it to the top since
it is the default.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Move all of the imply logic to default X if Y so it works again]
Signed-off-by: Tom Rini <trini@konsulko.com>
This converts the following to Kconfig:
CONFIG_ENV_IS_IN_MMC
CONFIG_ENV_IS_IN_NAND
CONFIG_ENV_IS_IN_UBI
CONFIG_ENV_IS_NOWHERE
In fact this already exists for sunxi as a 'choice' config. However not
all the choices are available in Kconfig yet so we cannot use that. It
would lead to more than one option being set.
In addition, one purpose of this series is to allow the environment to be
stored in more than one place. So the existing choice is converted to a
normal config allowing each option to be set independently.
There are not many opportunities for Kconfig updates to reduce the size of
this patch. This was tested with
./tools/moveconfig.py -i CONFIG_ENV_IS_IN_MMC
And then manual updates. This is because for CHAIN_OF_TRUST boards they
can only have ENV_IS_NOWHERE set, so we enforce that via Kconfig logic
now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
The boston memory map isn't suited to the simple "all memory starting
from 0" approach that the MIPS arch_fixup_fdt() implementation takes.
Instead we need to indicate the first 256MiB of DDR from 0 and the rest
from 0x90000000. Implement ft_board_setup to do that.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the MIPS Coherence Manager (CM) Global Configuration Registers
(GCRs) away from the region of the physical address space which the
Boston board's parallel flash is found in, such that we can access all
of flash without clobbering GCRs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Without adding a prompt for CONFIG_MIPS_CM_BASE, Kconfig doesn't allow
defconfigs to set it. Provide the prompt in order to allow for that.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This adds a new Kconfig option CONFIG_MIPS_INIT_STACK_IN_SRAM which
a SoC can select if it supports some kind of SRAM. Together with
CONFIG_SYS_INIT_SP_ADDR the initial stack and global data can be
set up in that SRAM. This can be used to provide a C environment
also for lowlevel_init().
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This adds a compile time option to include code for static
exception vectors. Static exception vectors are only needed,
when the U-Boot entry point is equal to the CPU reset exception
vector address. For instance this is the case when U-Boot is
used as ROM in Qemu or booted from parallel NOR flash. When
U-Boot is booted from RAM (e.g. loaded there by SPL), the
exception vectors need to be setup dynamically, which is done
in follow-up commits.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older MIPS Malta board.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Enable support for the MIPS Coherence Manager & L2 caches on the MIPS
Malta board, removing the need for us to attempt to bypass the L2 during
boot (which would fail with recent CPUs that expose L2 config via the CM
anyway).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Map the Global Control Registers (GCRs) provided by the MIPS Coherence
Manager (CM) in preparation for using some of them in later patches.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
MIPSfpga is an FPGA based dev platform.
In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks
The FPGA dev board used is the Nexys4DDR board by Digilent.
For more information, check the Readme file in board/imgtec/xilfpga
Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
For consistency with the other cache-related Kconfig entries & the
values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int
entry instead of a hex entry.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: 372286217f ("MIPS: Split I & D cache line size config")
Allow L1 Icache & L1 Dcache line size to be specified separately, since
there's no architectural mandate that they be the same. The
[id]cache_line_size functions are tidied up to take advantage of the
fact that the Kconfig entries are always present to simply check them
for zero rather than needing to #ifdef on their presence.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[removed CONFIG_SYS_CACHELINE_SIZE in include/configs/pic32mzdask.h]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Both real Malta boards & emulators that mimic Malta (eg. QEMU) can
support MIPS64 CPUs. Allow MIPS64 builds of U-Boot for such boards,
which enables the user to make use of the whole 64 bit address space.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Make use of device model & device tree to probe the UART driver. This is
the initial step in bringing Malta up to date with driver model, and
allows for cleaner handling of the different I/O addresses for different
system controllers by specifying the ISA bus address instead of a
translated memory address.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6
CPUs. Allow building U-Boot for such systems by selecting
CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way
that we currently select release 1 or release 2 targets. MIPSr6 is not
entirely backwards compatible with earlier releases of the architecture.
Some instructions are encoded differently, some are removed, some are
reused, so it is not practical to run U-Boot built for earlier revisions
on a MIPSr6 system. Update their Kconfig help text to reflect that.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Rather than having the values for CONFIG_SYS_CPU depend upon each
architecture revision, have them depend upon the more general
CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the
architecture revisions.
This is done in preparation for adding MIPSr6 support, which would
otherwise need to introduce new cases here.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This patch add some common code for QCA/Atheros ath79 SOCs such as
DDR tuning, chip reset and CPU detection.
Signed-off-by: Wills Wang <wills.wang@live.com>
The existing mips_io_port_base variable isn't suitable for use early
during boot since it will be stored in the .data section which may not
be writable pre-relocation. Fix this by moving the I/O port base address
into struct arch_global_data. In order to avoid adding this field for
all targets, make this dependant upon a new Kconfig entry
CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a
non-zero I/O port base, so select this option only for Malta.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Add Kconfig symbol for L1 cache shift like the kernel does.
The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source
for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS.
If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the
cache sizes are automatically detected and ARCH_DMA_MINALIGN
would be set to 128 Bytes.
The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which
corresponds to 32 Bytes. All current MIPS boards already used
that value. While on it, fix the Malta board to use a value of 6
like the kernel port does.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Move setup of -march to arch/mips/Makefile and follow the design on ARM.
Also add a possibility to chose specific CPU tune options.
Signed-off-by: Wills Wang <wills.wang@live.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.
Remove the configs that behave this way from the archs.
A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:
SPIFLASH
DISPLAY_BOARDINFO
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.
[1] http://prplfoundation.org/wiki/MIPS_documentation
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads & subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and defines that for existing mips32 targets. Exceptions are
malta where this is known to be unnecessary, and qemu-mips where caches
are not implemented.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
