This converts the following to Kconfig:
CONFIG_SPL_NAND_DRIVERS
CONFIG_SPL_NAND_ECC
CONFIG_SPL_NAND_SIMPLE
Signed-off-by: Adam Ford <aford173@gmail.com>
This converts the following to Kconfig:
CONFIG_ENV_OVERWRITE
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rerun migration, remove some comments]
Signed-off-by: Tom Rini <trini@konsulko.com>
Activate the new option -q in command "env info"
to avoid unnecessary trace during boot.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
cleanups
- fsl-crypto: RNG support and bug fixes
With OF_CONTROL disabled the build fails for
include/dm/read.h:932:10: error: ‘ENOTSUPP’ undeclared (first use in this function)
932 | return -ENOTSUPP;
Fixes: 45224e8f26 ("dm: core: gracefully handle alias seq without of")
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Some EP deivces need to initialize before RC scan it, e.g. NXP
layerscape platform, so add the init function in pci_ep uclass.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
If it is already instantiated tear it down first and then reinstanciate
it again with prediction resistance.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a
POR. Otherwise the RNG4 will throw an error.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Since Era 10, the version registers changed. Add the version registers
and use them on newer modules.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
We need the era in other modules, too. For example, to get the RNG
version.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Previous attempt to increase CONFIG_SYS_MALLOC_LEN was done in commit
c084a8edf4 ("configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size")
which increased malloc memory to ~1M.
PFE firmware alone requires 3M of dynamic memory allocation and
therefore, increase the config value to a larger value i.e 5M. This size
should be enough as of now to accommodate further memory requirements.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The eSDHC adapter card identification and multiplexing configuration
through FPGA had been implemented in both common mmc driver and
fsl_esdhc driver. However it is proper to move these code to board
files and do it during board initialization. The FPGA registers are
also board specific.
This patch is to move eSDHC adapter card identification and
multiplexing configuration from mmc driver to specific board files.
And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
[Rebased, Removed T1040QDS change as board does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Add xspi boot source to qixis command to let the soc boot from
flex-nor flash chip.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Remove "fdt_high" environment variable to use the bootm_size
to safely contain a kernel, device tree and initrd for
relocation.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This enables SYS_I2C_MXC to fix a bug that
failed to boot from sd card with
image u-boot-with-spl-pbl.bin
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Current PFE firmware access spi-nor memory directly. New spi-mem
framework does not support direct memory access. So, let's use
spi_flash_read API to access memory instead of directly using it.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
LS1088A-RDB has MMC, SCSI, DHCP as boot targets,
but the USB support was missing.
Add support for USB as Boot_targets_devices.
Signed-off-by: Era Tiwari <era.tiwari@nxp.com>
Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to
define it per board; the ls1028a_common.h is really board dependent and
only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE
when ARCH_LS1028A is selected.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Communication with some SPI slaves just won't cut it if these delays
(before the beginning, and after the end of a transfer) are not added to
the Chip Select signal.
These are a straight copy from Linux:
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
drivers/spi/spi-fsl-dspi.c
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Check the current ENV location, dynamically provided by the weak
function env_get_location to be sure that the environment can be
persistent.
The compilation flag ENV_IS_IN_DEVICE is not enough when the board
dynamically select the available storage location (according boot
device for example).
This patch solves issue for stm32mp1 platform, when the boot device
is USB.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Introduce UCLASS_SOC to be used for SOC identification and attribute
matching based on the SoC ID info. This allows drivers to be provided
for SoCs to retrieve SoC identifying information and also for matching
device attributes for selecting SoC specific data.
This is useful for other device drivers that may need different
parameters or quirks enabled depending on the specific device variant in
use.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This reverts commit 3ebe09d09a.
There is no user of this split function that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This reverts commit 118f4d4559.
There is no user of this split function that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.
Signed-off-by: Simon Glass <sjg@chromium.org>
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also
known as the RZ/G2M.
The kit consists of a SOM + Baseboard and supports microSD,
eMMC, Ethernet, a couple celular radios, two CAN interfaces,
Bluetooth and WiFi.
Signed-off-by: Adam Ford <aford173@gmail.com>
Add Kconfig entries for the dc2114x driver and convert various boards.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
This patch imports the device tree and required bindings to permit
the device tree to build for the R8Z774A1 (RZ/G2M).
Signed-off-by: Adam Ford <aford173@gmail.com>
- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
- Don't assume default value for offset and mask property.
- Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.
Enable SPI flash(SF) distro boot command in Sifive FU540.
This distro boot will read the boot script at specific
location at the flash and start sourcing the same.
Included the SF device at the last of the target devices
list since all the rest of the devices on the list have
more possibility to boot the distribution due to the
size of the SPI flash is concern.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
HiFive-Unleashed-A00 has SPI flash with 32MiB size.
So, let's use the script offset at the end of 4K.
This way it cannot overlap any offsets being used
by software components in flash layout.
So, SF distrocmd will pick the script at desired
script address and run.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
The series provides bug fixes for:
* crash in OS when accessing UEFI variables
* returning from UEFI fit images to U-Boot
* error handling for variable services provided by OP-TEE
* error handling in EFI_FILE_PROTOCOL.Read()
* missing function documentation
The first patches needed to use intermediate certificates for
secure boot are added. (The rest of the series requires
updating sbsigntool in our CI systems.)
Logging is enabled in the bootefi command.
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Merge tag 'efi-2020-10-rc1-5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc1 (5)
The series provides bug fixes for:
* crash in OS when accessing UEFI variables
* returning from UEFI fit images to U-Boot
* error handling for variable services provided by OP-TEE
* error handling in EFI_FILE_PROTOCOL.Read()
* missing function documentation
The first patches needed to use intermediate certificates for
secure boot are added. (The rest of the series requires
updating sbsigntool in our CI systems.)
Logging is enabled in the bootefi command.
- New rk3326 board: Hardkernel Odroid Go2;
- Update board config and dts for RockPI 4/N8/N10;
- Update led boot on support for roc-rk3399-pc;
- Enable SPI Flash suppor for rk3328 rock64 board;
- Update rockchip pcie phy to use generic framework;
Add console settings like stdin, stdout and stderr as
usbkbd and vidconsole respectively for evb-rk3288 targets.
This would certainly help to detect the attached video
devices (like HDMI) and print the console messages on display.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add default kernel_comp_addr_r and kernel_comp_size to support boot
from compressed kernel Image, this space is temporarily used during
decompress according to README.distro.
Reported-by: Tian Yuanhao <tianyuanhao@aliyun.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Also known as Odroid Go Advance but named Go2 internally by the
vendor it seems.
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The function, pkcs7_verify_one(), will be utilized to rework signature
verification logic aiming to support intermediate certificates in
"chain of trust."
To do that, its function interface is expanded, adding an extra argument
which is expected to return the last certificate in trusted chain.
Then, this last one must further be verified with signature database, db
and/or dbx.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
This function will be called from x509_check_for_self_signed() and
pkcs7_verify_one(), which will be imported from linux in a later patch.
While it does exist in linux code and has a similar functionality of
rsa_verify(), it calls further linux-specific interfaces inside.
That could lead to more files being imported from linux.
So simply re-implement it here instead of re-using the code.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Instead of adding the definition for the specific MM SVC used in
StandAloneMM we added the one used in the standard SMC calls.
So change the value from -4 to -5 to match the correct one defined in
EDK2 and rename them to avoid future confusion
Fixes 23a397d2e2: ("efi_loader: Add headers for EDK2 StandAloneMM communication")
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Introduce UCLASS_SOC to be used for SOC identification and attribute
matching based on the SoC ID info. This allows drivers to be provided
for SoCs to retrieve SoC identifying information and also for matching
device attributes for selecting SoC specific data.
This is useful for other device drivers that may need different
parameters or quirks enabled depending on the specific device variant in
use.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This reverts commit 3ebe09d09a.
There is no user of this split function that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This reverts commit 118f4d4559.
There is no user of this split function that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.
Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.
In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.
Hence, we disable the feature at probe time.
Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Allow keeping track of whether all CPUs have been enabled yet. This allows
us to know whether other CPUs need to be considered when updating
CPU-specific settings such as MTRRs on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.
Supported devices:
- UART
- reset
- CFI parallel NOR flash
Signed-off-by: Stefan Roese <sr@denx.de>
Add VendorID and DeviceID for supported devices on OcteonTX/TX2
platforms.
Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Since commit 4b0bcfa7c4 (Kconfig: Migrate CONFIG_BOOTM_* options),
the config_defaults.h file has been void of any actual content - and
these days, "sane defaults for everyone" is achieved by appropriate
default values in Kconfig. Remove it, and thus make every translation
unit process one less header file.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Some code was not converted by coccinelle, somehow.
I manually fixed up the remaining, and comments, README docs.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
[trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and
include/fdt_support.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:
It's a **mistake** to use typedef for structures and pointers.
Besides, using typedef for structures is annoying when you try to make
headers self-contained.
Let's say you have the following function declaration in a header:
void foo(bd_t *bd);
This is not self-contained since bd_t is not defined.
To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>
#include <asm/u-boot.h>
void foo(bd_t *bd);
Then, the include direcective pulls in more bloat needlessly.
If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:
struct bd_info;
void foo(struct bd_info *bd);
Right, typedef'ing bd_t is a mistake.
I used coccinelle to generate this commit.
The semantic patch that makes this change is as follows:
<smpl>
@@
typedef bd_t;
@@
-bd_t
+struct bd_info
</smpl>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
All configurations have been removed in 2016 by commit 7985cdf74b
("arm64: Remove non-full-va map code").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
These cases are typically fatal and are difficult to debug for random
users. Add checks for detecting overlapping images and abort if overlap
is detected.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
- New timer API to allow delays with a 32-bit microsecond timer
- Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core
- x86: Enable ACPI table generation by default
- x86: Enable the copy framebuffer on Coral
- x86: A few fixes to FSP2 with ApolloLake
- x86: Drop setup_pcat_compatibility()
- x86: Primary-to-Sideband Bus minor fixes
----------------
- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
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Merge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX for 2020.10
----------------
- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
This binding currently has a flags cell but it is not used. Make use of it
to create ACPI tables for interrupts.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
These registers need to be accesses from ACPI code, so move them to the
header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The P2SB bus needs to be hidden in some cases so that it does not get
auto-configured by Linux. Add a method for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
At present we can query the offset of a pinctrl register within the p2sb.
For ACPI we need to get the actual address of the register. Add a function
to handle this and rename the old one to more accurately reflect its
purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Allow writing named integers and strings to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix the "new blank line at EOF" warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Allow writing an ACPI device to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix build failures on Sandbox]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table
(NHLT).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow writing out a generic register.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
[bmeng: Fix build failures on Sandbox]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add a function to write a scope to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Fix build failures on Sandbox]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present only acpigen_write_integer() is exported for use by other code.
But in some cases it is useful to call the specific function depending on
the size of the value.
Export these functions and add a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Fix the "new blank line at EOF" warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.
Add core support for this, based on a structure which is built up through
calls to the driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Some devices such as GPIO need to override the normal path that would be
generated by driver model. Add a device-tree property for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Add support for accessing an entry's contents in memory-mapped SPI flash.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On x86 the SPI ROM can be memory-mapped, at least most of it. Add a way
to tell binman the offset from a ROM address to a RAM address.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a command that shows the individual blocks of data generated by each
device, effectively splitting the full table into its component parts.
This can be helpful for debugging.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
For many device types it is possible to figure out the name just by
looking at its uclass or parent. Add a function to handle this, since it
allows us to cover the vast majority of cases automatically.
However it is sometimes impossible to figure out an ACPI name for a device
just by looking at its uclass. For example a touch device may have a
vendor-specific name. Add a new "acpi,name" property to allow a custom
name to be created.
With this new feature we can drop the get_name() methods in the sandbox
I2C and SPI drivers. They were only added for testing purposes. Update the
tests to use the new values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function cannot currently be called on the root node. Add a check
for this as well as a test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some devices need to inject extra code into the Differentiated System
Descriptor Table (DSDT). Add a method to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in inject_dsdt() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Some devices need to generate code for the Secondary System Descriptor
Table (SSDT). Add a method to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a way for devices to enable and disable themselves using ACPI code
that updates GPIOs. This takes several timing parameters and supports
enable, reset and stop.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Power to some devices is controlled by GPIOs. Add a way to generate ACPI
code to enable and disable a GPIO so that this can be handled within an
ACPI method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These are used in ACPI to disable power to various pats of the system when
in sleep. Add a way to create a power resource, with the caller finishing
off the details.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add more functions to handle some miscellaneous ACPI opcodes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some drivers in Linux support both device tree and ACPI. U-Boot itself
uses Linux device-tree bindings for its own configuration but does not use
ACPI.
It is convenient to copy these values over to the ACPI DP table for
passing to linux. Add some convenience functions to help with this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allowing writing out a reference to a GPIO within the ACPI output. This
can be used by ACPI code to access a GPIO at runtime.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
More complex device properties can be provided to drivers via a
device-specific data (_DSD) object.
To create this we need to build it up in a separate data structure and
then generate the ACPI code, due to its recursive nature.
Add an implementation of this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI supports writing a UUID in a special format. Add a function to handle
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI supports storing names which are made up of multiple path components.
Several special cases are supported. Add a function to emit a name.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI supports storing a simple null-terminated string. Add support for
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI supports storing integers in various ways. Add a function to handle
this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
A package collects together several elements. Add an easy way of writing
a package header and updating its length later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
It is convenient to write a length value for preceding a block of data.
Of course the length is not known or is hard to calculate a priori. So add
a way to mark the start on a stack, so the length can be updated when
known.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function to write a SPI descriptor to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function to write a GPIO descriptor to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some devices use interrupts but some use GPIOs. Since these are fully
specified in the device tree we can automatically produce the correct ACPI
descriptor for a device.
Add a function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a function to write a GPIO descriptor to the generated ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Drop comment about the type always being ACPI_GPIO_TYPE_IO]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
