The lowest speed grade of Toradex AM62 SoMs is K speed, resulting in a
max value of 800MHz for the CPU operating frequency. A solution with
runtime selection of the CPU frequency is already planned to avoid these
kinds of problems in the future.
Fixes: 8fb8a6d499 ("arm: dts: k3-am625-verdin-r5:Change CPU frequency to 1000MHz")
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Since commit cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
the apalis-imx8qm board no longer boots.
The reason is that the imx8qm clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since commit cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
the colibri-imx8qxp board no longer boots.
The reason is that the imx8qxp clock driver does not handle the
LPUART IPG clocks inside get_rate(), set_rate() and enable() functions.
Fix the boot regression by adding the LPUART IPG entries.
Fixes: cc7df0b9e8 ("serial: lpuart: Enable IPG clock")
Reported-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X
Acked-by: Sean Anderson <seanga2@gmail.com>
The "Series-patchwork-url:" tag description says that it overrides the
settings file but doesn't specify the name of the setting. Elsewhere
in the documentation about the "useful" settings we see a setting that
sounds promising called "patchwork_server" that's actually not a valid
setting. It should be "patchwork_url".
Fix these problems so the doc is right and more useful.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
If bootefi selftest is executed and a problem with the device-tree
installation occurs, efi_install_fdt() writes sensible error messages.
It never returns EFI_INVALID_PARAMETER. It neither makes sense to check
for EFI_INVALID_PARAMETER nor to show the usage help for the bootefi
command in this case.
Fixes: 296faf4f7e ("cmd: bootefi: re-organize do_bootefi()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
If an EFI binary returns an error code EFI_INVALID_PARAMETER, we show the
usage help for the bootefi command:
Shell> exit 0x8000000000000002
## Application failed, r = 2
bootefi - Boots an EFI payload from memory
Usage:
bootefi <image address>[:<image size>] [<fdt address>]
- boot EFI payload
bootefi bootmgr [fdt address]
- load and boot EFI payload based on BootOrder/BootXXXX variables.
If specified, the device tree located at <fdt address> gets
exposed as EFI configuration table.
This makes no sense.
Fixes: 296faf4f7e ("cmd: bootefi: re-organize do_bootefi()")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
We should not try to remove protocol interfaces from a NULL handle.
efi_run_image() should always return the return code of the executed EFI
binary.
Fixes: 6422820ac3 ("efi_loader: split unrelated code from efi_bootmgr.c")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Update and improve the building documentation of Apalis iMX8.
The following changes were made:
- imx-atf repository changed to nxp-imx GitHub.
- imx-atf branch updated to 'lf_v2.6'.
- imx-seco updated to version 5.8.7.
- nxp-imx mfgtools link updated to GitHub releases.
- General writing improvements.
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Update and improve the building documentation of Colibri iMX8X.
The following changes were made:
- imx-atf repository changed to nxp-imx GitHub.
- imx-atf branch updated to 'lf_v2.6'.
- imx-seco updated to version 5.8.7.
- nxp-imx mfgtools link updated to GitHub releases.
- General writing improvements.
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.
This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream Linux.
Signed-off-by: Vitor Soares <vitor.soares@toradex.com>
Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Commit bfb3409d67 ("imx: toradex/apalis-imx8: correct SCU API usage")
made an incorrect logic change in the error code check of
sc_misc_otp_fuse_read():
- if (scierr == SC_ERR_NONE) {
+ if (scierr) {
/* QP has one A72 core disabled */
is_quadplus = ((val >> 4) & 0x3) != 0x0;
}
The other changes in this commit are correct.
sc_misc_otp_fuse_read() returns 0 on a successful fuse read.
This inversion causes board_mem_get_layout() to report incorrect RAM size.
Go back the original error check logic to fix the problem.
Fixes: bfb3409d67 ("imx: toradex/apalis-imx8: correct SCU API usage")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Commit aa6e698a7a ("imx: toradex/colibri-imx8x: correct SCU API usage")
made an incorrect logic change in the error code check of
sc_misc_otp_fuse_read():
- if (sc_err == SC_ERR_NONE) {
+ if (sc_err) {
/* DX has two A35 cores disabled */
return (val & 0xf) != 0x0;
}
The other changes in this commit are correct.
sc_misc_otp_fuse_read() returns 0 on a successful fuse read.
This inversion causes board_mem_get_layout() to report incorrect RAM size.
Go back the original error check logic to fix the problem.
Fixes: aa6e698a7a ("imx: toradex/colibri-imx8x: correct SCU API usage")
Reported-by: Hiago De Franco <hiago.franco@toradex.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-by: Hiago De Franco <hiago.franco@toradex.com> # Toradex Colibri iMX8X 1GB
define the phytec_get_som_type function also when the SoM detection is
disabled.
Fixes:
commit 110d321a56 ("board: phytec: common: phytec_som_detection: Add phytec_get_som_type")
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
- mips: fix bug in cache init on MIPS32r2 or later
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Merge tag 'mips-fixes-for-v2024.04' of https://source.denx.de/u-boot/custodians/u-boot-mips
- mips: implement __udivdi3 to fix building of SquashFS
- mips: fix bug in cache init on MIPS32r2 or later
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.
Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.
Reported by user ddqxy138 on Github.
b838586086
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Squashfs wasn't compiling because the lldiv() directives
turn into __udivdi3 and we are using private libgcc.
After this squashfs compiles for MIPS.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Bartel Eerdekens <barteleerdekens@gmail.com>
When copying the build system for Linux we missed to replace some
instances of 'Documentation' by 'doc'.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Python 3.6 introduced a DeprecationWarning for invalid escape sequences.
This is upgraded to a SyntaxWarning in Python 3.12, and will eventually
be a syntax error.
Fix these now to get ahead of it before it's an error.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Message-ID: <20230912060801.95533-3-bgray@linux.ibm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Adapted for U-Boot
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Use proper binary artifact names for HSFS devices.
Do not use the *_unsigned binaries.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
When using the previous prototype you got a compiler warning like this:
warning: initialization of 'int (*)(struct cmd_tbl *, int, int, char * const*)' from incompatible pointer type 'int (*)(struct cmd_tbl *, int, int, const char **)' [-Wincompatible-pointer-types]
Fixes: 3d9640f55c ("doc: expand README.commands")
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b
("efi_loader: create memory reservations in ACPI case")
broke boards that create additional memory reservations in
ft_board_setup() since it is now called before those additional
memory reservations are made. This is the case for the rk3588
boards and breaks booting OpenBSD on those boards.
Move the call back to its original location and add a call in
the code path used for ACPI.
Fixes: 1be415b21b ("efi_loader: create memory reservations in ACPI case")
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
The 'PolarFire Hart Software Services' SBI implementation returns the
version of the incorporated OpenSBI. Format the number accordingly.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
For an unknown implementation ID an output like
SBI 1.0Unknown implementation ID 16777216
Extensions:
sbi_set_timer
...
was shown. The number 16777216 is not the implementation ID.
* Show the correct number
* Use a hexadecimal output format
* Add a missing line feed
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Previously PLL node was missing from SPL dts. This caused BUS_ROOT
to stay on OSC clock (24Mhz). As a result, all peripherals have to
run at a much lower frequency, and loading from sdcard/emmc is slow.
Thus, enabling PLL node in dts to fix this.
Signed-off-by: Bo Gan <ganboing@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The first multi-letter extension after the single-letter extensions does
not have to be preceded by an underscore, which could cause the parser
to mistakenly find a single-letter extension after the start of the
multi-letter portion of the string.
Three letters precede multi-letter extensions (s, x & z), none of which
are valid single-letter extensions. The dt-binding also allows
multi-letter extensions starting with h, but no such extension have been
frozen or ratified, and the unprivileged spec no longer uses "h" as a
prefix for multi-letter hypervisor extensions, having moved to "sh"
instead. For that reason, modify the parser to stop at s, x & z to prevent
this overrun, ignoring h.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
U-Boot SPL loads the device-tree directly behind main U-Boot overlapping
the .bss section. reserve_fdt() is called in board_init_f() to relocate the
device-tree to a safe location.
Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in
the .bss section the device-tree is corrupted when _debug_uart_init() is
called in the SBI serial driver. Move the variable to the .data section.
Link: https://bugs.launchpad.net/ubuntu/+source/u-boot/+bug/2054091
Fixes: dfe0837494 ("risc-v: implement DBCN based debug console")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
It appears that there is some timing marginality either in the
board layout or the SoC that results in occasional data corruption
on some boards.
We observed this issue on some of the new HiFive Unmatched RevB
boards during volume production as well as some of the original
HiFive Unmatched boards from 2021 in our possession. This means
that there are other boards out there that might have the issue
too.
We have done some limited testing with DDR4 at 1600MT/s and
faulty boards (failing at 1866MT/s) passed.
We plan further testing after we procure a temperature chamber.
Signed-off-by: Thomas Perrot <thomas.perrot@bootlin.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Distro boot scripts are deprecated. Use standard boot instead.
Signed-off-by: Nam Cao <namcao@linutronix.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
- Use TF-A on imx8mp_beacon to fix boot regression.
- Use latest 6.8 dts for imx8mp_beacon.
- Fix the RAM initialization for phycore_imx8mp PCL-070 rev 1.
- Describe the 0087 i.mx8m mini product variant in tdx-cfg-block.
The device tree has evolved over time, so re-sync. This also
partial reverts one change on the PCIe, because U-Boot doesn't
have a proper driver. However, since the clock is configured
to generate a 100MHz reference clock by default, a proper driver
isn't really necessary.
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
When the board was originally added, it enabled some features which
allowed it to bypass Trusted Firmware, but as the feature set of
Linux grew and more features became available, the U-Boot config
options which bypassed TF-A caused issues, so it needs to return
to the standard operating mode of using TF-A or the system no
longer boots.
Fixes: ab53bd43db ("arm64: imx: Add support for imx8mp-beacon-kit")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
We need to differ between PCL-070 and PCM-070. PCL-070 supports 2GHz RAM
timings from pcb rev 1 or newer. PCM-070 supports 2GHz RAM timings from
pcb rev 3 or newer.
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
In case the PHY is fully described in DT, use PHY MDIO address
from DT directly instead of always using auto-detection. This
also fixes the behavior of 'mdio list' in such DT setup, which
now prints the PHY connected to the MAC correctly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
One fix makes the reboot more robust on some older board, another one
stabilises the initial clock setup on the A10/A20.
Two patches make sure our DRAM init does not actually change the content
of the DRAM array, which allows to use DRAM for Linux' pstore
functionality.
We get SPI support for U-Boot proper for one more SoC, that patch was
lingering around for a while, and should not affect other SoCs, so I am
merging this now.
As an added bonus, we get the defconfig file for a new board, the DT was
already synced from the kernel tree.
The CI looked happy with changes, and I tested them on five different
boards with different SoCs.
