On OMAP platforms, SATA controller provides the SCSI subsystem
so implement scsi_init().
Get rid of the unnecessary sata_init() call from dra7xx-evm
and omap5-uevm board files.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Commit 12cc543767 'omap3: overo: Select
fdtfile for expansion board' wrongly missed the operator in the fdtfile
test. Update the test to only overwrite an empty fdtfile environment
variable.
Signed-off-by: Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
SCIF of koelsch use external clock mode.
This enables external clock mode on koelsch board.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
SCIF of lager use external clock mode.
This enables external clock mode on lager board.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
The clock of SCIF (serial port) of lager is supplied from External
Clock. And value of clock is 14.7456MHz.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Enable this feature to support driver model before relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Change this board to add a device tree.
This also adds a pinmux header file although it is not used as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Most of the smdkv310 features are common with other exynos4 boards. To
permit easier addition of driver model support, use the common file and
add a device tree file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Most of the arndale features are common with other exynos5250 boards. To
permit easier addition of driver model support, use the common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so
move the settings into a separate common file to be used by those that need
it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
A few things are common but are not in the common file. Fix this and
rename the file to fit with the other exynos*-common files.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Since exynos4 and exyno5 share many settings, we should move these into
a common file to avoid duplication.
In effect the changes are that all exynos boards now have EXT4 and FAT
write support. This affects exynos5250 and exynos5420 which previously
did not. This also disables the ext2 commands which are equivalent to
ext4 anyway.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
We want exynos5250-dt.h to be a board which can support any exynos5250
device. This matches the naming used by Linux. As a first step, rename
the existing -dt files to -common to make it clear they are common files,
and not specific boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With the driver model conversion we are going to be using driver model for
SPI and not for I2C. This works OK so long as a board doesn't need both
dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow
uses I2C we need to split the configs so that only one driver is compiled
for each platform.
We can fix this later when driver model supports I2C.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards
cannot due to a hardware design decision. Select the correct driver to use
in each case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Things run faster when the data cache is enabled, so turn it on along with
the 'dcache' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Support reading/writing ext4 partitions.
Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Enable 'fastboot' command.
This is currently enabled but not yet functional. Including it in the
configuration will ease further testing and development as discussed
on the mailing list.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Some users (QNX and Windows CE users in particular) have asked
to disable the Penguin shown on the display at boot time.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Increase the maximum number of arguments allowed by the Hush parser.
This prevents errors when users or scripts aren't quoting parameters
when setting the "bootargs" variable et al.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Enable the "i2c edid" command to query data from an attached
HDMI monitor.
Usage is typically this:
U-Boot > i2c dev 1
U-Boot > i2c edid 0x50
...
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
If no boot script was found, expose internal storage over the
USB mass storage gadget to allow easy programming.
This is especially useful when SD cards are inaccessible or when
loading SATA drives.
More details are available in this blog post:
http://boundarydevices.com/u-boot-usb-mass-storage-gadget/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Remove the individual attempts to load using ext2 and fat, replace with the
generic load command supporting available filesystem types.
Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
This patch enables boot to USB storage devices by expanding on the list
of boot devices.
Because the USB startup currently takes a long time, it places USB at
the end of the list of supported devices.
You can over-ride the boot order using the bootdevs environment variable.
For instance, this will make USB the first (highest priority) device:
U-Boot > setenv bootdevs usb mmc sata
U-Boot > saveenv
Signed-off-by: Diego Rondini <diego.rondini@kynetics.it>
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Add support for the USB mass storage to enable access to on-board
storage (especially eMMC and SATA).
Details at:
http://boundarydevices.com/u-boot-usb-mass-storage-gadget/
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
filesystem type into the environment.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.
This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.
Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.
Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit
Signed-off-by: Chin Liang See <clsee@altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Fixed the L4 MP clock divider and synced the clock code with latest
rocketboards codebase (thanks Dinh for pointing this out)
Like many platforms, the Altera socfpga platform requires that the
preloader be "signed" in a certain way or the built-in boot ROM will
not boot the code.
This change automatically creates an appropriately signed preloader
from an SPL image.
The signed image includes a CRC which must, of course, be generated
with a CRC generator that the SoCFPGA boot ROM agrees with otherwise
the boot ROM will reject the image.
Unfortunately the CRC used in this boot ROM is not the same as the
Adler CRC in lib/crc32.c. Indeed the Adler code is not technically a
CRC but is more correctly described as a checksum.
Thus, the appropriate CRC generator is added to lib/ as crc32_alt.c.
Signed-off-by: Charles Manning <cdhmanning@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
V2: - Zap unused constant
- Explicitly print an error message in case of error
- Rework the hdr_checksum() function to take the *header directly
instead of a plan buffer pointer
Remove this symbol from configs, since it's unused.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Chin Liang See <clsee@altera.com>
The DMA descriptors used by the DW MMC block must be aligned to cacheline
size, otherwise we are unable to properly flush/inval cache over them and
we get data corruption.
The reason I chose this approach of expanding the structure is because
the driver allocates the descriptors in bulk. This approach does waste
space by inserting slop inbetween the descriptors, but it makes access
to the descriptors easy as the compiler does know the real size of the
structure. It also makes cache operations easy, since the size of the
structure is cache aligned and the structure start address is as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Acked-by: Pavel Machek <pavel@denx.de>
Get rid of the line-over-80 problems and zap the typedef that
went alongside those enums.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
This patch adds support for the OT1200 series of devices.
Following components are used in u-boot:
+ ethernet
+ i2c
+ emmc
+ gpio
For more details see README.
Changes v1 > v2
- make use of enable_cspi_clock(..)
- fix usage of OUTPUT_40OHM define
- added README
Changes v2 > v3
- improve spelling in README
- added own copy of mx6q_4x_mt41j128.cfg
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
PERST_GPIO and POWER_GPIO are currently swapped.
Fix the GPIO assignments as per the board schematics.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Besides converting the LS-XHL and LS-CHLv2 to generic board, fix a typo
which accidentally reverted the bootsource to 'hdd' although the default
bootsource should be 'legacy'.
Cc: Tom Rini <trini@ti.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Siemens boards are now using DFU in fullspeed only. For
this CONFIG_USB_GADGET_DUALSPEED is undefined.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Liu Bin <b-liu@ti.com>
Cc: Lukas Stockmann <lukas.stockmann@siemens.com>
Use the new force parameter to make the stdio_deregister succeed, replacing
stdin with a nulldev, and assume that the usb keyboard will come back after
the reset.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In some cases we really want to move forward with a deregister, add a force
parameter to allow this, and replace the dev with a nulldev in this case.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch add MTDIDS and MTDPARTS defaults settings to sheevaplug
Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Changes in v1:
- add MTDIDS and MTDPARTS default to sheevaplug
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
This patch move the environment offset in sheevaplug.
The size of the u-boot binary is become too big.
Fix saving environments was result of corrupting the u-boot.
Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Changes in v2:
- patch description
Changes in v1:
- fix sheevaplug environment offset
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Update the ddr scripts for LPDDR2 and add two build configs for LPDDR2
arm2 board. Since the LPDDR2 arm2 board has different DDR size, use
CONFIG_DDR_MB in defconfig to replace the PHYS_SDRAM_SIZE.
Signed-off-by: Ye.Li <B37916@freescale.com>
This patch adds the i.MX6DL arm2 board support. The i.MX6DL ARM2
shared the same board with i.MX6Q ARM2 board since the i.MX6DL is
pin-pin compatible with i.MX6Q.
The patch also support the DDR 32-BIT mode option. Please define
CONFIG_DDR_32BIT in the board configure file to enable DDR 32-BIT
mode.But due to the board design, it's 64bit DDR buswidth physically,
so, if you CONFIG_DDR_32BIT, the DDR memory size will be half of it.
Signed-off-by: Ye.Li <B37916@freescale.com>
Enable the CONFIG_CMD_FS_GENERIC on m53evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Enable the CONFIG_CMD_FS_GENERIC on m28evk to avoid per-fs specific commands
and tweak the environment to cater for this new option.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Make sure the boot.scr exists on the card before loading it
from the card to avoid annoying message on the console.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
1. Set the image load partition to the first FAT partition.
2. Set the kernel rootfs partition to the second partition.
Signed-off-by: Ye.Li <B37916@freescale.com>
To support loading FDT file for kernel, add the fdt address,
file and loading script to arm2 board default environment.
Signed-off-by: Ye.Li <B37916@freescale.com>
Some of the #defines in spi.h are not bracketed. To avoid future mistakes
add brackets. Also add an explanatory comment for SPI_CONN_DUAL_...
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Sandbox may as well support everything. This increases the amount of code
that is built/tested by sandbox, and also provides access to all the
supported SPI flash devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
Spin table is at the very beginning of boot code. Each core has an individual
release address within the spin table, the ft_cpu_setup fn updates the
"cpu-release-addr" property of each cpu node with the corresponding release
address.
Also fix CPU_RELEASE_ADDR to point to secondary_boot_func.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
of_bus_default_count_cells can be used to get the #address-cells
and #size-cells defined by the current node's parent node. This
is required when using of_read_number to read from FDT nodes that
can be 32 or 64 bytes depending on values defined by the parent.
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
This is being done so that it can be used outside 'fdt_support.c'. Making
life more convenient when reading device node properties that can be 32
or 64 bits long.
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.
Signed-off-by: York Sun <yorksun@freescale.com>
DP-DDR is used for DPAA, separated from main memory pool for general
use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit).
Signed-off-by: York Sun <yorksun@freescale.com>
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.
Signed-off-by: York Sun <yorksun@freescale.com>
Add support of NOR and NAND flash for simulator target.
Here
IFC - CS0: NOR flash
IFC - CS1: NAND flash
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This option specifies the default Device Tree used for the run-time
configuration of U-Boot.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Michal Simek <michal.simek@xilinx.com>
This commit moves:
CONFIG_OF_CONTROL
CONFIG_OF_SEPARATE
CONFIG_OF_EMBED
CONFIG_OF_HOSTFILE
Because these options are currently not supported for SPL,
the "Device Tree Control" menu does not appear in the SPL
configuration.
Note:
zynq-common.h should be adjusted so as not to change the
default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
The libc headers on FreeBSD and likely related projects as well contain an
header file, cdefs.h which provides similiar functionality as linux/compiler.h.
It provides compiler independent defines like __weak __packed, to allow
compiling with multiple compilers which might have a different syntax for such
extension.
Since that header file is included in multiple standard headers, like stddef.h
and stdarg.h, multiple definitions of those defines will be present if both are
included. When compiling u-boot the compiler will warn about it hundreds of
times since e.g. common.h will include both files indirectly.
commit 7ea50d5284 "compiler_gcc: do not redefine
__gnu_attributes" prevented such redefinitions, but this was undone by commit
fb8ffd7cfc "compiler*.h: sync
include/linux/compiler*.h with Linux 3.16".
Add the checks back where necessary to prevent such warnings.
As the original patch this checkpatch warning is ignored:
"WARNING: Adding new packed members is to be done with care"
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Acked-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Since clang has a different definition for uninitialized_var
it will complain that it is redefined in include/compiler.h.
Since these are already defined in linux/compiler.h just remove
this instance.
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
The section name and the C variable name seem to be opposite.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Now config_cmd_defaults.h is empty so it can be deleted safely.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since CONFIG_CMD_IMPORTENV is defined in config_cmd_defaults.h,
it should be enabled for all the boards except bf506f-ezkit
that undefs it explicitely.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since CONFIG_CMD_GO is defined in config_cmd_defaults.h
(and no board undefs it its own header), it can be moved to
Kconfig with the default value "y".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since CONFIG_CMD_EXPORTENV is defined in config_cmd_defaults.h,
it should be enabled for all the boards except bf506f-ezkit
that undefs it explicitely.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since CONFIG_CMD_CRC32 is defined in config_cmd_defaults.h,
it is enabled for all the boards except the ones undefining it
explicitly:
kwb
tseries_mmc
tseries_nand
tseries_spi
vct_platinum_onenand_small
vct_platinum_small
vct_platinumavc_onenand_small
vct_platinumavc_small
vct_premium_onenand_small
vct_premium_small
The default value of this config option should be "y" and
"# CONFIG_CMD_CRC32 is not set" should be added for those exceptions.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
CONFIG_CMD_BOOTM is defined in config_cmd_defaults.h
which is forcebly included from each board.
So, the default value of "config CMD_BOOTM" should be "y".
For some boards undefining it (bf506f-ezkit, controlcenterd_TRAILBLA,
controlcenterd_TRAILBLAZER_DEVELOP, controlcenterd_TRAILBLAZER),
"# CONFIG_CMD_BOOTM is not set" should be added to their defconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
If this option is enabled, the objects under lib/ directory
are compiled with speed optimization, not size optimization.
(Currently, only used by some Blackfin boards.)
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Scsi disks need to be probed before we try to access them, otherwise all
accesses fail with: ** Bad device size - scsi 0 **.
Reported-by: Karsten Merker <merker@debian.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Karsten Merker <merker@debian.org>
One of the I2C EEPROM is used to store/save and edit mac
addresses of ports.
this patch add required CONFIG to support the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
CPC1 is not being enabled by default as powerpc is supposed to
use only CPC2. Though by editing hwconfig en_cpc option,
CPC1 can also be enabled.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.
This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
to alternate banks from vBank0 to vBank4 and vice versa
This patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI board
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support of rcw for T1042RDB, it makes following changes :
- Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB
- Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates
comments for valid serdes protocol which is 0x06
- Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable the Extend address to support SPI flash more than 16MB.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Currently, CONFIG_SPL_SPI_* #defines are used for controlling SPI boot in
SPL. These #defines do not allow the user to select SPI mode for the SPI flash
(there's no CONFIG_SPL_SPI_MODE, so the SPI mode is hardcoded in
spi_spl_load.c), and duplicate information already provided by
CONFIG_SF_DEFAULT_* #defines.
Kill CONFIG_SPL_SPI_*, and use CONFIG_SF_DEFAULT_* instead.
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Hannes Petermaier <hannes.petermaier@br-automation.com>
Cc: Michal Simek <monstr@monstr.eu>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
MXC SPI driver has a feature whereas a GPIO line can be used to force CS high
across multiple transactions. This is set up by embedding the GPIO information
in the CS value:
cs = (cs | gpio << 8)
This merge of cs and gpio data into one value breaks the sf probe command:
if the use of gpio is required, invoking "sf probe <cs>" will not work, because
the CS argument doesn't have the GPIO information in it. Instead, the user must
use "sf probe <cs | gpio << 8>". For example, if bank 2 gpio 30 is used to force
cs high on cs 0, bus 0, then instead of typing "sf probe 0" the user now must
type "sf probe 15872".
This is inconsistent with the description of the sf probe command, and forces
the user to be aware of implementaiton details.
Fix this by introducing a new board function: board_spi_cs_gpio(), which will
accept a naked CS value, and provide the driver with the relevant GPIO, if one
is necessary.
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Eric Benard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Let's enable CONFIG_SYS_GENERIC_BOARD in order to get rid of warnings related
to generic board support is not in place.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Sabrelite board has two solts: 0 is SD3 (bottom) slot and 1 is uSD4 (top) slot.
This patch makes use of both slots instead of only one.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
Reviewed-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
Let's enable CONFIG_SYS_GENERIC_BOARD in order to get rid of warnings related
to generic board not being supported.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We should not hardcode CONFIG_NETMASK in the config file.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage' for OMAP4 boards.
This allows to use EXT partition instead of FAT, while keeping FAT compatibility.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
Copy them from Linux v3.16 tag.
My main motivation of this commit is to add compiler-clang.h.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
U-Boot has imported various source files from other projects,
mostly Linux.
Something like
#ifdef __UBOOT__
[ modification for U-Boot ]
#else
[ original code ]
#endif
is an often used strategy for clarification of adjusted parts,
that is, easier re-sync in future.
Instead of defining __UBOOT__ in each source file,
passing it from the top Makefile would be easier.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR.
USDHC3 and USDHC4 are both initialized in board_mmc_init. There is
no restriction on USDHC3 addr or USDHC4 addr should be assigned to
CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid
errors when fsl_esdhc_mmc_init is invoked.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used
in board_mmc_init.
If board_mmc_init failed, cpu_mmc_init->fsl_esdhc_mmc_init will use
CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to
correct value.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This adds NAND support for the Vybrid tower system (TWR-VF65GS10)
provided by the vf610_nfc driver. Full 16-Bit bus width is
supported. Also an aditional config vf610twr_nand is introduced
which gets the environment from NAND. However, booting U-Boot from
NAND is not yet possible due to missing boot configuration block
(BCB).
Signed-off-by: Stefan Agner <stefan@agner.ch>
Use driver model for serial ports.
Since Tegra now uses driver model for serial, adjust the definition of
V_NS16550_CLK so that it is clear that this is only used for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.
The console alias needs to be set up to indicate which port is used for
the console.
Also add a binding file since this is missing.
Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console
Signed-off-by: Simon Glass <sjg@chromium.org>
Add driver model support so that ns16550 can support operation both with
and without driver model.
The driver needs a clock frequency so cannot stand alone unfortunately. The
clock frequency must be provided by a separate driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Adjust the sandbox serial driver to use the new driver model uclass. The
driver works much as before, but within the new framework.
Signed-off-by: Simon Glass <sjg@chromium.org>
Serial devices support simple byte input/output and a few operations to find
out whether data is available. Add a basic uclass for serial devices to be
used by drivers that are converted to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Within /chosen we may have a node which points to another node, similar
to how /aliases works. Add a helper function to do this lookup.
Signed-off-by: Simon Glass <sjg@chromium.org>
This is an implementation of GPIOs for Tegra that uses driver model. It has
been tested on trimslice and also using the new iotrace feature.
The implementation uses a top-level GPIO device (which has no actual GPIOS).
Under this all the banks are created as separate GPIO devices.
The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7,
..., Z0..Z7, AA0..AA7, etc.
Since driver model is not yet available before relocation, or in SPL, a
special function is provided for seaboard's SPL code.
Signed-off-by: Simon Glass <sjg@chromium.org>
For some boards board_init() will change GPIOs, so we need to have driver
model available before then. Adjust the board init to arrange this, but
enable it for driver model only, just to be safe.
This does create additional #ifdef logic, but it is safer than trying to
make a pervasive change which may cause some boards to break.
Signed-off-by: Simon Glass <sjg@chromium.org>
The microblaze-generic board fails to build at least
with the kernel.org crosstool:
https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_microblaze-linux.tar.xz
$ make CROSS_COMPILE=microblaze-linux- microblaze-generic_defconfig all
[ snip ]
CC disk/part.o
CC disk/part_dos.o
LD disk/built-in.o
CC drivers/block/systemace.o
{standard input}: Assembler messages:
{standard input}:2495: Error: operation combines symbols in different segments
{standard input}:2496: Error: operation combines symbols in different segments
{standard input}:2499: Error: operation combines symbols in different segments
{standard input}:2500: Error: operation combines symbols in different segments
{standard input}:2505: Error: operation combines symbols in different segments
{standard input}:2506: Error: operation combines symbols in different segments
{standard input}:2515: Error: operation combines symbols in different segments
{standard input}:2516: Error: operation combines symbols in different segments
{standard input}:2519: Error: operation combines symbols in different segments
{standard input}:2520: Error: operation combines symbols in different segments
{standard input}:2529: Error: operation combines symbols in different segments
{standard input}:2530: Error: operation combines symbols in different segments
{standard input}:2533: Error: operation combines symbols in different segments
{standard input}:2534: Error: operation combines symbols in different segments
{standard input}:2539: Error: operation combines symbols in different segments
{standard input}:2540: Error: operation combines symbols in different segments
{standard input}:2549: Error: operation combines symbols in different segments
{standard input}:2550: Error: operation combines symbols in different segments
make[3]: *** [drivers/block/systemace.o] Error 1
make[2]: *** [drivers/block] Error 2
make[1]: *** [drivers] Error 2
make: *** [__build_one_by_one] Error 2
It looks like the cause of this error message is the "#ident" directive.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
