The PHY reset GPIOs were missing from the DT, add them.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
If the clock framework provides the driver with valid clock,
enable them, otherwise the SCIF might not work if the clock
are not enabled prior to the driver probe.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add support for obtaining PHY reset GPIO from DT and toggling it
before configuring the PHY to put the PHY into defined state.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The SDxCKCR must be configured correctly, otherwise the SDIF can be
unstable. This is done in board files thus far, but those are going
away, so move the setting of SDxCKCR into the correct place.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Place the stack right below U-Boot so it's not in the way in case
U-Boot grows too much.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Just move those config options from macros to configs.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This adds the following commits from upstream:
fe50bd1ecc1d fdtget: Split out cell list display into a new function
62d812308d11 README: Add a note about test_tree1.dts
5bed86aee9e8 pylibfdt: Add support for fdt_subnode_offset()
46f31b65b3b3 pylibfdt: Add support for fdt_node_offset_by_phandle()
a3ae43723687 pylibfdt: Add support for fdt_parent_offset()
a198af80344c pylibfdt: Add support for fdt_get_phandle()
b9eba92ea50f tests: Return a failure code when any tests fail
155faf6cc209 pylibfdt: Use local pylibfdt module
50e5cd07f325 pylibfdt: Add a test for use of uint32_t
ab78860f09f5 pylibfdt: Add stdint include to fix uint32_t
36f511fb1113 tests: Add stacked overlay tests on fdtoverlay
1bb00655d3e5 fdt: Allow stacked overlays phandle references
a33c2247ac8d Introduce fdt_setprop_placeholder() method
0016f8c2aa32 dtc: change default phandles to ePAPR style instead of both
e3b9a9588a35 tests: fdtoverlay unit test
42409146f2db fdtoverlay: A tool that applies overlays
aae22722fc8d manual: Document missing options
13ce6e1c2fc4 dtc: fix sprintf() format string error, again
d990b8013889 Makefile: Fix build on MSYS2 and Cygwin
51f56dedf8ea Clean up shared library compile/link options
21a2bc896e3d Suppress expected error message in fdtdump test
2a42b14d0d03 dtc: check.c fix compile error
a10cb3c818d3 Fix get_node_by_path string equality check
548aea2c436a fdtdump: Discourage use of fdtdump
c2258841a785 fdtdump: Fix over-zealous version check
9067ee4be0e6 Fix a few whitespace and style nits
e56f2b07be38 pylibfdt: Use setup.py to build the swig file
896f1c133265 pylibfdt: Use Makefile constructs to implement NO_PYTHON
90db6d9989ca pylibfdt: Allow setup.py to operate stand-alone
e20d9658cd8f Add Coverity Scan support
b04a2cf08862 pylibfdt: Fix code style in setup.py
1c5170d3a466 pylibfdt: Rename libfdt.swig to libfdt.i
580a9f6c2880 Add a libfdt function to write a property placeholder
ab15256d8d02 pylibfdt: Use the call function to simplify the Makefile
9f2e3a3a1f19 pylibfdt: Use the correct libfdt version in the module
e91c652af215 pylibfdt: Enable installation of Python module
8a892fd85d94 pylibfdt: Allow building to be disabled
741cdff85d3e .travis.yml: Add builds with and without Python library prerequisites
14c4171f4f9a pylibfdt: Use package_dir to set the package directory
89a5062ab231 pylibfdt: Use environment to pass C flags and files
4e0e0d049757 pylibfdt: Allow pkg-config to be supplied in the environment
6afd7d9688f5 Correct typo: s/pylibgfdt/pylibfdt/
756ffc4f52f6 Build pylibfdt as part of the normal build process
8cb3896358e9 Adjust libfdt.h to work with swig
b40aa8359aff Mention pylibfdt in the documentation
12cfb740cc76 Add tests for pylibfdt
50f250701631 Add an initial Python library for libfdt
cdbb2b6c7a3a checks: Warn on node name unit-addresses with '0x' or leading 0s
4c15d5da17cc checks: Add bus checks for simple-bus buses
33c3985226d3 checks: Add bus checks for PCI buses
Signed-off-by: Tom Rini <trini@konsulko.com>
This adds the following commits from upstream:
558cd81bdd43 dtc: Bump version to v1.4.4
c17a811c62eb fdtput: Remove star from value_len documentation
194d5caaefcb fdtget: Use @return to document the return value
d922ecdd017b tests: Make realloc_fdt() really allocate *fdt
921cc17fec29 libfdt: overlay: Check the value of the right variable
9ffdf60bf463 dtc: Simplify asm_emit_string() implementation
881012e44386 libfdt: Change names of sparse helper macros
bad5b28049e5 Fix assorted sparse warnings
672ac09ea04d Clean up gcc attributes
49300f2ade6a dtc: Don't abuse struct fdt_reserve_entry
Signed-off-by: Tom Rini <trini@konsulko.com>
Using the update-dtc-source.sh script from Linux v4.14-rc1 import the
portions of dtc that we require. We bring in update-dtc-source.sh and
scripts/dtc/Makefile from Linux v4.14-rc1. Rework DTC_FLAGS handling to
not require a test.
Signed-off-by: Tom Rini <trini@konsulko.com>
For EFI boot GPT partition table support is needed as well
as the part command and also the SPL needs to fallback to
other boot methods after parse the SPL header.
Signed-off-by: Frank Kunz <mailinglists@kunz-im-inter.net>
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the
NAND initialization process is driven by the driver itself.
CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
PPA loading during SPL stage is not required for nornal
SD boot scenario.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
PPA loading during SPL stage is not required for nornal
SD boot scenario.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Current u-boot disables IFC support for SD boot on all ls1043a
boards. Actually IFC only conflicts with QSPI on ls1043a hardware.
Only when QSPI is used, IFC should be disabled. Otherwise,
the u-boot with ls1043aqds_sdcard_ifc_defconfig would not work.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As per current implementation, default value of board env is
based on board filename i.e ls2080ardb.
With distro support changes, this env is used to decide upon
kernel dtb which is different for other SoCs (ls2088a, ls2081a)
combination supported with this board.
Add support to modify board env at runtime based on SoC type
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For most of ls2080ardb use-cases, mc private DRAM block is required
to be of 1.75GB.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: this reservation needs to be reduced if memory is not enough]
Reviewed-by: York Sun <york.sun@nxp.com>
Commit 0aaa1a9 added support for LS208xA devices but fixing
iommu-map property is missing. This patch adds support for
fixing iommu-map.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
As per updated board design, different QSPI flash
is connected on boards, hence change QSPI flash type
from Micron n25q512a device to spansion s25fs512s
device in dts and config.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
the prints of boardinfo late in cycle during uboot boot.
This feature is not required in case of QSPI_BOOT.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In the TI SOCs a PBIAS cell exists to provide a bias voltage to the MMC1
IO cells. Without this bias voltage these I/O cells can not function
properly. The PBIAS cell is controlled by software.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
dev_read_string_count() is used to get the number of strings in a
stringlist.
dev_read_string_index() is used to get a string in the stringlist based on
its position in the list.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Add OF match entries and quirks for Renesas RCar Gen3 controllers
into the driver. The IP this driver handles is in fact Matsushita
one and in used both in Socionext and Renesas chips.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Check if the OF match has any associated data and if so, use those
data as the controller quirks, otherwise fallback to the old method
of reading the controller version register to figure out the quirks.
This allows us to supply controller quirks on controllers which ie.
do not have version register.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
The Renesas RCar Gen3 contains the same controller, originally
Matsushita. This patch adds support for handling of the 64bit
FIFO on this controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
The Renesas RCar Gen3 contains the same controller, originally
Matsushita, yet the register addresses are shifted by 1 to the
left. The whole controller is also 64bit, including the data
FIFOs and RSP registers. This patch adds support for handling
the register IO by shifting the register offset by 1 in the IO
accessor functions.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
This patch prepares the driver to support controller(s) with registers
at locations shifted by constant. Pull out the readl()/writel() from
the driver into separate functions, where the adjustment of the register
offset can be easily contained.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
With support for overlays and calling the -@ flag to dtc we need to have
at least 1.4.3 available now.
Cc: Simon Glass <sjg@chromium.org>
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
from incompatible pointer type [-Wincompatible-pointer-types]
src, &length))
Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
CC: Jean-Jacques Hiblot <jjhiblot@ti.com>
This patch provides default implementations of the two functions
set_uart_mux_conf and set_mux_conf_regs. Hence boards not using
them do not need to provide their distinct empty definitions.
Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch adds support for stm32h7 soc family, stm32h743
discovery and evaluation boards.
For more information about STM32H7 series, please visit:
http://www.st.com/en/microcontrollers/stm32h7-series.html
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :
_ Add RCC clock driver node and update all clocks phandle
accordingly.
By default, on kernel side, all clocks was temporarly
configured as a phandle to timer_clk waiting for a RCC
clock driver to be available.
On U-boot side, we now have a dedicated RCC clock driver, we
can configured all clocks as phandle to this driver.
All this binding update will be available soon in a kernel tag,
as all the bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
_ Align STM32H7 serial compatible string with the one which will be
available in next kernel tag. The bindings has been acked by
Rob Herring [2].
This compatible string will be usefull to add stm32h7 specific
feature for this serial driver.
[2] https://lkml.org/lkml/2017/7/17/739
_ Add gpio compatible and aliases for stm32h743
_ Add FMC sdram node with associated new bindings value to
manage second bank (ie bank 1).
_ Add missing HSI and CSI oscillators nodes needed
by STM32H7 RCC clock driver.
Clock sources could be:
_ HSE (High Speed External)
_ HSI (High Speed Internal)
_ CSI (Low Power Internal)
These clocks can be used as clocksource in some configuration.
By default, HSE is selected as clock source.
_ Set HSE to 25Mhz for stm32h743i-disco and eval board
By default, the external oscillator frequency is defined at
25 Mhz in SoC stm32h743.dtsi file.
It has been set at 125 Mhz in kernel DT temporarly waiting for
RCC clock driver becomes available.
As in U-boot we got a RCC clock driver, the real value of HSE
clock can be used.
_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
pwrcfg and gpio nodes.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This file is imported from linux kernel v4.13
Add device tree support for STM32H743 evaluation board.
This board offers :
_ STM32H743XIH6 microcontroller with 2 Mbytes of
Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
_ 5.7” 640x480 TFT color LCD with touch screen
_ Ethernet compliant with IEEE-802.3-2002
_ USB OTG HS and FS
_ I2 C compatible serial interface
_ RTC with rechargeable backup battery
_ SAI Audio DAC
_ ST-MEMS digital microphones
_ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
_ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash
_ 1-Gbit Twin Quad-SPI NOR Flash
_ Potentiometer
_ 4 colored user LEDs
_ Reset, wakeup, tamper or key buttons
_ Joystick with 4-direction control and selector
_ Board connectors :
Power jack
3 USB with Micro-AB
RS-232 communications
Ethernet RJ45
FD-CAN compliant connection
Stereo headset jack including analog microphone input
2 audio jacks for external speakers
microSD™ card
JTAG/SWD and ETM trace
_ Expansion connectors:
Extension connectors and memory connectors for daughterboard
or wire-wrap board
_ Flexible power-supply options: ST-LINK USB VBUS or external
sources
_ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
capability: mass storage, virtual COM port and debug port
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All these files are imported from linux kernel v4.13
Add device tree support for STM32H743 SoC and discovery
board. This board offers :
_ STM32H743XIH6 microcontroller with 2 Mbytes of
Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
_ 5.7” 640x480 TFT color LCD with touch screen
_ Ethernet compliant with IEEE-802.3-2002
_ USB OTG HS
_ I2 C compatible serial interface
_ ST-MEMS digital microphones
_ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
_ 8Mx32bit SDRAM
_ 1-Gbit Twin Quad-SPI NOR Flash
_ Reset, wakeup, or key buttons
_ Joystick with 4-direction control and selector
_ Board connectors :
1 USB with Micro-AB
Ethernet RJ45
Stereo headset jack including analog microphone input
microSD™ card
RCA connector
JTAG/SWD and ETM trace
_ Expansion connectors:
Arduino Uno compatible Connectors
2 x PIO connectors (PMOD and PMOD+)
_ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
capability: mass storage, virtual COM port and debug port
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds the support of reset and clock control
block (rcc) found on STM32 SoCs.
This driver is similar to a MFD linux driver.
This driver supports currently STM32H7 only.
STM32F4 and STM32F7 will be migrated to this rcc MFD driver
in the future to uniformize all STM32 SoCs already upstreamed.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.
This driver doesn't implement .of_match as it's binded
by MFD RCC driver.
To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.
This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver implements basic clock setup, only clock gating
is implemented.
This driver doesn't implement .of_match as it's binded
by MFD RCC driver.
Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].
[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
STM32F7 and STM32H7 shares the same UART block, add
STM32H7 compatible string.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
STM32H7 SoCs uses the same pinctrl block as found into
STM32F7 SoCs
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Since we may jump to next stage like ATF/OP-TEE instead of U-Boot,
we need to stash the bootstage info before it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add usb_gadget_handle_interrupts(), board_usb_init(),
board_usb_cleanup() and g_dnl_board_usb_cable_connected()
callbacks needed for FASTBOOT support
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
